Memory controller chipset

• US 6,822,654 B1
• Filed: 12/31/2001
• Issued: 11/23/2004
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Takahashi, Yutaka, Ligon, David, Arnold, Vaughn Todd, Iwamoto, Derek Fujio, Bratt, Joseph P., Benkual, Jack, Trivedi, Sushma Shrikant, Weybrew, Steven Todd
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US10/038,700
• Time in Patent Office: 1,058 Days
• Field of Search: 345/519, 345/520, 345/531, 345/502-505, 345/559, 345/557, 345/568, 345/536-538, 345/522, 345/501, 711/141-146, 711/104, 710/100, 710/305-313, 710/260
• US Class Current: 345/520
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.

Claims

1. At least one chip of a chipset in a computer system having at least one host processor and a host memory, the chip comprising:

an interconnect;

a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access;

a host interface coupled to the interconnect, the host interface providing access to the host processor; and

a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media, wherein the media processor includes

a compute engine to process multiple media data, and

a stream interface coupled to the compute engine, the stream interface including

a cache coherent interface, wherein the requests sent to the host processor from the compute engine are snooped by the host processor'"'"'s caches, and

a cache non-coherent interface, wherein the requests are sent to the host memory directly from the compute engine.

2. The chip of claim 1, wherein the media processor processes multiple media data streams substantially simultaneously, and wherein each of the media data streams comprises a time related sequence of data representing related images.

3. The chip of claim 1, wherein the media processor processes multiple media data autonomously and asynchronously to the host processor.

4. The chip of claim 1, further comprising an interrupt mechanism, wherein the media processor communicates with the host processor through the interrupt mechanism.

5. The chip of claim 4, wherein the interrupt mechanism is controlled by a software program executed by the host processor.

6. The chip of claim 1, wherein the host processor accesses the media processor through a set of memory-mapped registers.

7. The chip of claim 1, wherein the media processor further comprises:

a chip interconnect for coupling the compute engine and the stream interface, wherein the stream interface receives and distributes requests between the compute engine and the rest of the computer system.

8. The chip of claim 7, further comprising multiple compute engines coupled to the chip interconnect, the multiple compute engines processing multiple media data substantially simultaneously.

9. The chip of claim 8, wherein the multiple compute engines communicate with each other through a compute engine-to-compute engine interface or through compute engine-to-compute engine interfaces.

10. The chip of claim 7, wherein the host processor accesses the compute engine through a set of memory-mapped registers.

11. The chip of claim 10, wherein the set of memory-mapped registers defines a command queue and wherein commands or routines are sent to the compute engine.

12. The chip of claim 7, wherein the stream interface comprises a memory mapping mechanism, the memory mapping mechanism translating a logical address to a physical address for snooping and accessing memory.

13. The chip of claim 12, wherein the memory mapping mechanism further determines attributes to control cache coherency.

14. The chip of claim 12, wherein the memory mapping mechanism comprises a video address re-mapping table (VART).

15. The chip of claim 12, wherein the logical address can be located at a system address space which is shareable with the host processor.

16. The chip of claim 1, further comprising a first peripheral component interconnect (PCI) interface coupled to the interconnect and a second PCI interface coupled to the interconnect.

17. The chip of claim 16, wherein the first PCI interface is an accelerated graphics port (AGP), wherein the AGP is configured to be coupled to an external graphics controller.

18. The chip of claim 16, wherein the second PCI interface is configured to be coupled to a PCI device, or the second PCI interface is configured to be coupled to an input/output (I/O) controller.

19. The chip of claim 18, further comprising:

a universal serial bus (USB) coupled to the I/O controller;

a networking device coupled to the I/O controller; and

an EEE-1394 bus coupled to the I/O controller.

20. The chip of claim 1, further comprising:

a universal serial bus (USB) interface coupled to the interconnect;

a network interface coupled to the interconnect; and

an EEE-1394 bus interface coupled to the interconnect.

21. A computer system having a chip according to claim 1.

22. The computer system of claim 21, further comprising multiple host processors.

23. The computer system of claim 21, is a network computer.

24. At least one chip of a chipset in a computer system having at least one host processor and a host memory, the chip comprising:

an interconnect;

a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access;

a host interface coupled to the interconnect, the host interface providing access to the host processor; and

a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media, wherein the media processor includes

a chip interconnect,

a compute engine coupled to the chip interconnect, the compute engine processing multiple media data autonomously and asynchronously to the host processor, and

a stream interface coupled to the chip interconnect, the stream interface receiving and distributing requests between the compute engine and the rest of the computer system, wherein the stream interface includes

a cache coherent interface, wherein the requests sent to the host processor from the compute engine are snooped by the host processor'"'"'s caches,

a cache non-coherent interface, wherein the requests are sent to the host memory directly from the compute engine, and

a master interface, wherein the host processor controls the compute engine through the master interface.

25. The chip of claim 24, wherein the host processor controls the compute engine through a set of memory mapped addresses.

26. At least one chip of a chipset in a computer system having at least one host processor and a host memory, the chip comprising:

an interconnect;

a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access;

a host interface coupled to the interconnect, the host interface providing access to the host processor; and

a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media, wherein the media processor includes

a chip interconnect,

a compute engine coupled to the chip interconnect, the compute engine processing multiple media data autonomously and asynchronously to the host processor, and

a stream interface coupled to the chip interconnect, the stream interface receiving and distributing requests between the compute engine and the rest of the computer system, wherein the compute engine includes

an input/output (I/O) interface, the I/O interface receiving and transmitting control and data to/from the compute engine,

a local memory for storing the data,

at least one functional unit,

at least one instruction unit, and

at least one register file.

27. The chip of claim 26, wherein the compute engine further comprises a direct memory access (DMA) mechanism transferring the data between the local memory location and the host memory.

28. The chip of claim 26, wherein the local memory is accessible by another compute engine.

29. The chip of claim 26, wherein the at least one functional unit comprises:

an instruction/branch unit;

an integer arithmetic/logic unit (IALU);

an integer shift unit (ISHU);

a load/store unit (LSU);

a vector permute unit (VPU);

a vector simple integer unit (VSIU);

a vector complex integer unit (VCIU); and

a vector look-up table unit (VLUT).

30. The chip of claim 29, wherein the at least one functional unit further comprises a floating point unit (FPU) and a vector floating point unit (VFPU).

31. The chip of claim 29, wherein the instruction/branch unit further comprises a cache memory storing an instruction stream.

32. The chip of claim 29, wherein the vector look-up table unit further comprises storage location storing at least one look-up table.

33. The chip of claim 26, wherein the at least one functional unit comprises multiple functional units of a kind.

34. The chip of claim 26, wherein the at least one register file comprises:

a general purpose register file;

a vector register file; and

a special purpose register file.

35. The chip of claim 26, wherein the at least one register file is a multi-ported register file.