Voltage controlled oscillator with frequency stabilized and PLL circuit using the same

• US 6,825,731 B2
• Filed: 03/22/2002
• Issued: 11/30/2004
• Est. Priority Date: 03/27/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Hasegawa, Masaru
• Primary Examiner(s): NGUYEN, MINH T
• Application Number:
  US10/104,859
• Publication Number:
  US 20020140504A1
• Time in Patent Office: 984 Days
• Field of Search: 331/34, 331/46, 331/48, 331/50, 331/57, 331/175, 331/177.R, 331/185, 331/DIG.2, 327/280, 327/281, 327/147, 327/156-163, 375/373-376
• US Class Current: 331/57
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/023 by the use of differential amplifiers or comparators, with internal or external positive feedback
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A voltage controlled oscillator includes N (N is an integer equal to or more than 2) inversion-type differential amplifiers and a level converter. The N (N is an integer equal to or more than 2) inversion-type differential amplifiers are connected in a loop such that each of output signals outputted from one of the N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of the N inversion-type differential amplifiers. The level converter is connected to one of the N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate an oscillation signal from the output signals outputted from the last inversion-type differential amplifier. Each of the N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage.

Claims

1. A voltage controlled oscillator comprising:

N (N is an integer equal to or more than

     2) inversion-type differential amplifiers connected in a loop such that each of output signals outputted from one of said N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of said N inversion-type differential amplifiers; and

a level converter connected to one of said N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate an oscillation signal from the output signals outputted from said last inversion-type differential amplifier, and

wherein each of said N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage, and either of said voltages is directly connected to a single element in each of said N inversion-type differential amplifiers, each of said single elements having one terminal grounded.

2. The voltage controlled oscillator according to claim 1, wherein operation current of each of said N inversion-type differential amplifiers is determined based on said predetermined voltage and said control voltage.

3. The voltage controlled oscillator according to claim 2, wherein said operation current of each of said N inversion-type differential amplifiers is directly determined based on a summation of a current determined based on said predetermined voltage and a current determined based on said control voltage.

4. The voltage controlled oscillator according to claim 1, wherein an offset of a frequency of said oscillation signal is set based on said predetermined voltage.

5. The voltage controlled oscillator according to claim 1, wherein a frequency of said oscillation signal is determined based on said control voltage with a predetermined voltage range.

6. The voltage controlled oscillator according to claim 5, wherein said frequency of said oscillation signal is proportional to said control voltage with said predetermined voltage range.

7. The voltage controlled oscillator according to claim 1, further comprising:

a bias generator which improves current drive ability of said N inversion-type differential amplifiers.

8. A voltage controlled oscillator comprising:

N (N is an integer equal to or more than

     2) inversion-type differential amplifiers connected in a loop such that each of output signals outputted from one of said N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of said N inversion-type differential amplifiers; and

a level converter connected to one of said N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate an oscillation signal from the output signals outputted from said last inversion-type differential amplifier, and

wherein each of said N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage,

wherein each of said N inversion-type differential amplifiers comprises;

a differential section connected to a higher power supply voltage and including a pair of differential operation transistors to operate a differential amplifying operation;

a first current source transistor connected between said differential section and a lower power supply voltage and having a gate supplied with a predetermined voltage; and

a second current source transistor connected between said differential section and said lower power supply voltage in parallel to said first current source transistor and having a gate supplied with a control voltage.

9. The voltage controlled oscillator according to claim 8, further comprising:

a bias generator which controls the differential amplifying operation of each of said N inversion-type differential amplifiers based on said predetermined voltage.

10. The voltage controlled oscillator according to claim 9, wherein said bias generator comprises:

a first drive transistor connected to said lower power supply voltage and having a gate electrode supplied with said predetermined voltage; and

a specific transistor connected between said higher power supply voltage and said first drive transistor, and having a gate thereof connected with a drain electrode thereof to be driven by said first drive transistor such that said specific transistor controls the differential amplifying operation of each of said N inversion-type differential amplifiers.

11. The voltage controlled oscillator according to claim 10, wherein said differential section of each of said N inversion-type differential amplifiers comprises:

a pair of first and second load transistors provided for a corresponding one of said differential operation transistors, wherein said first load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to a drain thereof, and said second load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to said drain of said specific transistor.

12. The voltage controlled oscillator according to claim 11, wherein said specific transistor and said second load transistor constitute a current mirror circuit.

13. The voltage controlled oscillator according to claim 10, wherein said bias generator further comprises:

a second drive transistor connected between said lower power supply voltage and said specific transistor in parallel to said first drive transistor and having a gate electrode supplied with said control voltage, and

wherein said specific transistor is driven by said second drive transistor in addition to said first drive transistor such that said specific transistor controls the differential amplifying operation of each of said N inversion-type differential amplifiers.

14. The voltage controlled oscillator according to claim 13, wherein said differential section of each of said N inversion-type differential amplifiers comprises:

a pair of first and second load transistors provided for a corresponding one of said differential operation transistors, wherein said first load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to a drain thereof, and said second load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to said drain of said specific transistor.

15. The voltage controlled oscillator according to claim 14, wherein said specific transistor and said second load transistor constitute a current mirror circuit.

16. The voltage controlled oscillator according to claim 8, wherein said differential section of each of said N inversion-type differential amplifiers comprises:

a resistance provided for a corresponding one of said differential operation transistors, and connected between said higher power supply voltage and said corresponding differential operation transistor.

17. A voltage controlled oscillator for generating an oscillation signal, comprising:

offset means for determining an offset frequency based on a predetermined voltage; and

proportion means for controlling a frequency of said oscillation signal to be proportional to a control voltage, and

wherein the frequency of said oscillation signal is directly determined based on the predetermined voltage and the control voltage, and

wherein the voltage control oscillator has N inversion-type differential amplifiers, and each of said inversion-type differential amplifiers is directly connected at a single element to either the control voltage or the predetermined voltage.

18. A phase locked loop (PLL) circuit comprising:

a phase frequency comparator which compares a reference signal and a feedback signal and generate a difference signal based on the comparison result;

a control voltage generating section which generates a control voltage in response to said difference signal;

a voltage controlled oscillator which generates an oscillation signal based on said control voltage and a predetermined voltage; and

a frequency divider which carries out a frequency division to said oscillation signal outputted from said voltage controlled oscillator to produce said feedback signal,

wherein said voltage controlled oscillator comprises;

N (N is an integer equal to or more than

     2) inversion-type differential amplifiers connected in a loop such that each of output signals outputted from one of said N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of said N inversion-type differential amplifiers; and

a level converter connected to one of said N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate said oscillation signal from the output signals outputted from said last inversion-type differential amplifier, and

wherein each of said N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage, and either of said voltages is directly connected to a single element in each of said N inversion-type differential amplifiers, each of said single elements having one terminal grounded.

19. The PLL circuit according to claim 18, wherein operation current of each of said N inversion-type differential amplifiers is directly determined based on a summation of a current determined based on said predetermined voltage and a current determined based on said control voltage.

20. The PLL circuit according to claim 18, further comprising:

a bias generator which improves current drive ability of said N inversion-type differential amplifiers.

21. A phase locked loop (PLL) circuit comprising:

a phase frequency comparator which compares a reference signal and a feedback signal and generate a difference signal based on the comparison result;

a control voltage generating section which generates a control voltage in response to said difference signal;

a voltage controlled oscillator which generates an oscillation signal based on said control voltage and a predetermined voltage; and

a frequency divider which carries out a frequency division to said oscillation signal outputted from said voltage controlled oscillator to produce said feedback signal,

wherein said voltage controlled oscillator comprises;

N (N is an integer equal to or more than

     2) inversion-type differential amplifiers connected in a loop such that each of output signals outputted from one of said N inversion-type differential amplifiers has an opposite polarity to a corresponding one of output signals outputted from the next one of said N inversion-type differential amplifiers; and

a level converter connected to one of said N inversion-type differential amplifiers as a last inversion-type differential amplifier to generate said oscillation signal from the output signals outputted from said last inversion-type differential amplifier, and

wherein each of said N inversion-type differential amplifiers operates in response to a predetermined voltage and a control voltage,

wherein each of said N inversion-type differential amplifiers comprises;

a differential section connected to a higher power supply voltage and including a pair of differential operation transistors to operate a differential amplifying operation;

a first current source transistor connected between said differential section and a lower power supply voltage and having a gate supplied with a predetermined voltage; and

a second current source transistor connected between said differential section and said lower power supply voltage in parallel to said first current source transistor and having a gate supplied with a control voltage.

22. The PLL circuit according to claim 21, further comprising:

a bias generator which controls the differential amplifying operation of each of said N inversion-type differential amplifiers based on said predetermined voltage.

23. The PLL circuit according to claim 22, wherein said bias generator comprises:

a first drive transistor connected to said lower power supply voltage and having a gate electrode supplied with said predetermined voltage; and

a specific transistor connected between said higher power supply voltage and said first drive transistor, and having a gate thereof connected with a drain electrode thereof to be driven by said first drive transistor such that said specific transistor controls the differential amplifying operation of each of said N inversion-type differential amplifiers.

24. The PLL circuit according to claim 23, wherein said differential section of each of said N inversion-type differential amplifiers comprises:

a pair of first and second load transistors provided for a corresponding one of said differential operation transistors, wherein said first load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to a drain thereof, and said second load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to said drain of said specific transistor.

25. The PLL circuit according to claim 24, wherein said specific transistor and said second load transistor constitute a current mirror circuit.

26. The PLL circuit according to claim 23, wherein said bias generator further comprises:

a second drive transistor connected between said lower power supply voltage and said specific transistor in parallel to said first drive transistor and having a gate electrode supplied with said control voltage, and

wherein said specific transistor is driven by said second drive transistor in addition to said first drive transistor such that said specific transistor controls the differential amplifying operation of each of said N inversion-type differential amplifiers.

27. The PLL circuit according to claim 26, wherein said differential section of each of said N inversion-type differential amplifiers comprises:

a pair of first and second load transistors provided for a corresponding one of said differential operation transistors, wherein said first load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to a drain thereof, and said second load transistor is connected between said higher power supply voltage and said corresponding differential operation transistor and has a gate connected to said drain of said specific transistor.

28. The PLL circuit according to claim 27, wherein said specific transistor and said second load transistor constitute a current mirror circuit.

29. The PLL circuit according to claim 21, wherein said differential section of each of said N inversion-type differential amplifiers comprises:

a resistance provided for a corresponding one of said differential operation transistors, and connected between said higher power supply voltage and said corresponding differential operation transistor.