Receiver, transceiver circuit, signal transmission method, and signal transmission system

• US 6,826,390 B1
• Filed: 07/12/2000
• Issued: 11/30/2004
• Est. Priority Date: 07/14/1999
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka
• Primary Examiner(s): Corsaro, Nick
• Assistant Examiner(s): TRINH, TAN H
• Application Number:
  US09/614,907
• Time in Patent Office: 1,602 Days
• Field of Search: 455/226.1, 455/334, 455/280, 455/296, 455/311, 455/232.1, 455/234.1, 455/234.2, 375/346, 375/355
• US Class Current: 455/226.1
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45762 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45986 using switching means, e.g. sample and hold
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/1461 Suppression of signals in the return path, i.e. bidirectional control circuits
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Claims

1. A receiver comprising:

an offset application circuit for applying an offset to an input signal;

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit; and

a timing control circuit for controlling decision timing in said decision circuit by shifting said decision timing relative to said input signal.

2. The receiver as claimed in claim 1, wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal.

3. The receiver as claimed in claim 2, further comprising:

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes.

4. The receiver as claimed in claim 1, wherein said offset application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

5. The receiver as claimed in claim 1, wherein said offset application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

6. The receiver as claimed in claim 1, wherein received signal quality of said input signal is diagnosed, or a characteristic of said receiver or driver is adjusted, by using the waveform of said input signal obtained from said known offset and the result output from said decision circuit.

7. A receiver comprising:

an offset application circuit for applying an offset to an input signal;

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal;

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes; and

a timing control circuit for controlling decision timing in said decision circuit in such a manner as to vary said decision timing relative to an internal clock in said receiver, and wherein the level of said offset is adjusted by judging an externally supplied, predetermined test pattern at output timing of said timing control circuit, and information concerning said input signal is acquired using said input signal level detection circuit.

8. A receiver comprising:

an offset application circuit for applying an offset to an input signal;

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit, wherein said offset voltage application circuit passes a constant current to a termination resistor provided in parallel to an input terminal of said receiver.

9. A receiver comprising:

an offset application circuit for applying an offset to an input signal;

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit, wherein said offset voltage application circuit includes a plurality of capacitors and switches, and varies the level of said offset by varying a precharge voltage of each of said capacitors.

10. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying an offset to said input signal;

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said offset and on a result output from said decision circuit; and

a timing control circuit for controlling decision timing in said decision circuit by shifting said decision timing relative to said input signal.

11. The transceiver circuit as claimed in claim 10, wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal.

12. The transceiver circuit as claimed in claim 11, wherein said receiver further comprises:

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes.

13. The transceiver circuit as claimed in claim 10, wherein said offset application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

14. The transceiver circuit as claimed in claim 10, wherein said offset application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

15. The transceiver circuit as claimed in claim 10, wherein received signal quality of said input signal is diagnosed, or a characteristic of said receiver or driver is adjusted, by using the waveform of said input signal obtained from said known offset and the result output from said decision circuit.

16. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying an offset to said input signal, wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal;

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit;

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes; and

a timing control circuit for controlling decision timing in said decision circuit in such a manner as to vary said decision timing relative to an internal clock in said receiver, wherein the level of said offset is adjusted by judging an externally supplied, predetermined test pattern at an output timing of said timing control circuit, and information concerning said input signal is acquired using said input signal level detection circuit.

17. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying an offset to said input signal; and

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit,

wherein said offset voltage application circuit passes a constant current to a termination resistor provided in parallel to an input terminal of said receiver.

18. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying an offset to said input signal; and

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit,

wherein said offset voltage application circuit includes a plurality of capacitors and switches, and varies the level of said offset by varying a precharge voltage of each of said capacitors.

19. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying an offset to said input signal; and

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit,

the transceiver circuit further comprising;

a test pattern transmitting circuit for transmitting a predetermined test pattern from said driver to a receiver in another transceiver circuit;

a test pattern judging circuit for receiving, by said receiver, a test pattern transmitted from a driver in another transceiver circuit and for judging said received test pattern at a predetermined timing using said decision circuit; and

a test pattern level detection circuit for detecting the level of said test pattern by adjusting the level of said offset, and wherein an equalization parameter of said receiver is adjusted using an output of said test pattern level detection circuit.

20. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying an offset to said input signal; and

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit,

the transceiver circuit, further comprising;

a boundary signal transmitting circuit for transmitting from said driver to a receiver in another transceiver circuit a boundary signal which should be judged to be at a boundary between data “

0” and

“

1”

; and

a boundary offset seeking circuit for receiving, by said receiver, a boundary signal transmitted from a driver in another transceiver circuit and for seeking such a boundary offset that the result of a decision in said decision circuit agrees with the boundary between data “

0” and

“

1”

, and wherein zero adjustment of said receiver is performed by applying said boundary offset to said receiver at the time of usual input signal reception.

21. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying an offset to said in input signal; and

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit,

the transceiver circuit, further comprising;

a test pattern transmitting circuit for transmitting a predetermined test pattern from said driver to a receiver in another transceiver circuit;

a receive timing changing test pattern level detection circuit for receiving, by said receiver, a test pattern transmitted from a driver in another transceiver circuit by sequentially changing a receive timing in said receiver and for detecting the level of said test pattern; and

an operation circuit for adjusting a parameter of said transceiver circuit by using an output of said receive timing changing test pattern level detection circuit.

22. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal; and

said receiver includes an offset application circuit for applying an offset to said input signal, a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said offset and on a result output from said decision circuit, and a timing control circuit for controlling decision timing in said decision circuit by shifting said decision timing relative to said input signal.

23. The signal transmission system as claimed in claim 22, wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal.

24. The signal transmission system as claimed in claim 22, wherein said receiver further includes:

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes.

25. The signal transmission system as claimed in claim 22, wherein said offset application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

26. The signal transmission system as claimed in claim 22, wherein said offset application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

27. The signal transmission system as claimed in claim 22, wherein received signal quality of said input signal is diagnosed, or a characteristic of said receiver or driver is adjusted, by using the waveform of said input signal obtained from said known offset and the result output from said decision circuit.

28. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal; and

said receiver includes an offset application circuit for applying an offset to said input signal and a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit,

wherein said receiver further includes;

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes; and

a timing control circuit for controlling decision timing in said decision circuit in such a manner as to vary said decision timing relative to an internal clock in said receiver, wherein the level of said offset is adjusted by judging an externally supplied, predetermined test pattern at output timing of said timing control circuit, and information concerning said input signal is acquired using said input signal level detection circuit.

29. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal; and

said receiver includes an offset application circuit for applying an offset to said input signal and a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit, wherein said offset voltage application circuit passes a constant current to a termination resistor provided in parallel to an input terminal of said receiver.

30. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal; and

said receiver includes an offset application circuit for applying an offset to said input signal and a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit, wherein said offset voltage application circuit includes a plurality of capacitors and switches, and varies the level of said offset by varying a precharge voltage of each of said capacitors.

31. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal;

said receiver includes an offset application circuit for applying an offset to said input signal and a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit;

a predetermined test pattern is transmitted from said driver in said first transceiver circuit, said test pattern is judged at predetermined timing using said receiver in said second transceiver circuit; and

the level of said test pattern is detected by adjusting the level of said offset in said second transceiver circuit, thereby adjusting an equalization parameter of said receiver in said second transceiver circuit.

32. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal;

said receiver includes an offset application circuit for applying an offset to said input signal and a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit;

a boundary signal which should be judged to be at a boundary between data “

0” and

“

1”

is transmitted to said receiver in said second transceiver circuit by said driver in said first transceiver circuit;

said boundary signal is received by said receiver in said second transceiver circuit and such a boundary offset is sought so that the result of a decision in said decision circuit of said receiver agrees with the boundary between data “

0” and

“

1”

; and

zero adjustment of said receiver in said second transceiver circuit is performed by applying said boundary offset to said receiver at the time of usual input signal reception.

33. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal;

said receiver includes an offset application circuit for applying an offset to said input signal and a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit;

a predetermined test pattern is transmitted to said receiver in said first transceiver circuit by said driver in said first transceiver circuit; and

said test pattern is received by said receiver in said second transceiver circuit by sequentially changing the receive timing in said receiver and the level of said test pattern is detected, thereby adjusting a parameter of said second transceiver circuit.

34. A receiver comprising:

an offset application circuit for applying an offset to an input signal;

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said offset and on a result output from said decision circuit; and

an offset level control circuit for increasing or decreasing the level of said offset to detect a change of an output of said decision circuit.

35. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal; and

said receiver includes an offset application circuit for applying an offset to said input signal, a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said offset and on a result output from said decision circuit, and an offset level control circuit for increasing or decreasing the level of said offset to detect a change of an output of said decision circuit.