Method of manufacturing a trench transistor having a heavy body region

• US 6,828,195 B2
• Filed: 01/17/2003
• Issued: 12/07/2004
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean Edward, Mo, Brian Sze-Ki, Chau, Duc, Sapp, Steven, Bencuya, Izak
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US10/347,254
• Publication Number:
  US 20030127688A1
• Time in Patent Office: 690 Days
• Field of Search: 438/270-272, 438/589
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1. A method of manufacturing a trench transistor comprising:

providing a semiconductor substrate having dopants of a first conductivity type;

forming a plurality of trenches extending to a first depth into the semiconductor substrate;

lining each of the plurality of trenches with a gate dielectric material;

substantially filling each dielectric-lined trench with conductive material;

forming a doped well in the substrate to a second depth that is less than said first depth of the plurality of trenches, the doped well having dopants of a second conductivity type opposite to said first conductivity type;

forming a heavy body extending inside the doped well to a third depth that is less than said second depth of said doped well, the heavy body having dopants of the second conductivity type and forming an abrupt junction with the well; and

forming a source region inside the well, the source region having dopants of the first conductivity types.

2. The method of claim 1 wherein the step of forming a doped well forms the well with a substantially flat bottom.

3. The method of claim 1 further comprising forming a deep doped region having dopants of the second conductivity type, the deep doped region extending into the substrate to a fourth depth that is deeper than said first depth of the trench.

4. The method of claim 3 wherein the step of forming a deep doped region forms a PN junction diode with the substrate that helps improve a breakdown voltage of the transistor.

5. The method of claim 3 wherein the deep doped region forms a termination structure around the periphery of the substrate.

6. The method of claim 1 wherein the step of substantially filling each dielectric-lined trench leaves a recess at an upper portion of each trench.

7. The method of claim 6 further comprising filling the recess at the upper portion of each trench with dielectric material.

8. The method of claim 1 wherein the step of forming the heavy body comprises a double implant process.

9. The method of claim 8 wherein the double implant process comprises:

a first implant of dopants of the first conductivity type, at a first energy level and a first dosage to form a first doped portion of the heavy body; and

a second implant of dopants of the first conductivity type, at a second energy level and a second dosage to form a second doped portion of the heavy body.

10. The method of claim 9 wherein the first implant occurs at approximately the third depth.

11. The method of claim 9 wherein the first energy level is higher than the second energy level.

12. The method of claim 11 wherein the first dosage is higher than the second dosage.

13. The method of claim 1 wherein the step of forming the heavy body comprises a process of diffusing dopants of the second conductivity type.

14. The method of claim 1 wherein the step of forming the heavy body comprises using a continuous dopant source at the surface of the semiconductor substrate.

15. The method of claim 1 wherein the step of forming a plurality of trenches comprises patterning and etching the plurality of trenches that extend in parallel along a longitudinal axis.

16. The method of claim 15 further comprising forming a contact area on the surface of the substrate between adjacent trenches.

17. The method of claim 16 wherein the step of forming the contact area comprises forming alternating source contact regions and heavy body contact regions.

18. The method of claim 16 wherein the step of forming the contact area comprises forming a ladder-shaped source contact region surrounding heavy body contact regions.

19. The method claim 18 wherein the step of forming the ladder-shaped source contact region surrounding heavy body contact regions, comprises:

forming a source blocking mask on the surface of the semiconductor substrate patterned to cover the heavy body contact regions; and

implanting dopants of the first conductivity type to form the ladder-shaped source contact region.

20. The method of claim 18 wherein the step of forming the ladder-shaped source contact region surrounding heavy body contact regions, comprises forming a dielectric layer on the surface of the semiconductor substrate patterned to expose the heavy body contact regions.

21. A method of manufacturing a trench field effect transistor on a semiconductor substrate having dopants of a first conductivity type, the method comprising:

etching a plurality of trenches into the semiconductor substrate to a first depth;

lining the plurality of trenches with dielectric layer;

substantially filling the dielectric-lined plurality of trenches with conductive material;

forming a well between adjacent trenches to a second depth that is shallower than the first depth, the well having dopants of second conductivity type opposite to the first conductivity type;

forming a heavy body inside the well to a third depth that is shallower than the second depth, the heavy body having dopants of the second conductivity type; and

forming a source region inside the well and adjacent to trenches, the source region having dopants of the first conductivity type,

wherein, the step of forming a heavy body employs a process to form an abrupt junction between the heavy body and the well at approximately the third depth.

22. The method of claim 21 further comprising adjusting a location of the abrupt junction relative to the depth of the well so that a transistor breakdown current is spaced away from the trench in the semiconductor.

23. The method of claim 21 further comprising forming a deep doped region having dopants of the second conductivity type, the deep doped region extending into the substrate to a fourth depth that is deeper than said first depth of the trench.