Edge termination in a trench-gate MOSFET

• US 6,833,583 B2
• Filed: 09/10/2002
• Issued: 12/21/2004
• Est. Priority Date: 09/13/2001
• Status: Expired due to Term

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Inʼt Zandt, Michael A. A., Hijzen, Erwin A., Hueting, Raymond J. E.
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US10/238,795
• Publication Number:
  US 20030047777A1
• Time in Patent Office: 833 Days
• Field of Search: 257/329, 257/330, 257/331, 257/488, 257/492, 257/493, 438/270
• US Class Current: 257/329
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

To avoid premature breakdown at the edge of the active area of RESURF trench-gate MOS device, an edge field plate (24) can be placed with a connection to the gate and a second spaced field plate (24) in the same trench (12). The gate trench network (12) could be either formed by hexagon unit cells or by square unit cells. Since the RESURF condition requires a small cell pitch, self-aligned processing could be used.

Claims

1. A cellular trench-gate field-effect transistor comprises a semiconductor body having an array of transistor cells, the cells being bounded by a pattern of perimeter trenches lined with dielectric material around the perimeter of the array, the perimeter trenches having an inner wall closer to an active area of the transistor and an outer wall closer to the edge of the transistor, wherein each of said inner and outer walls has a field plate located on the dielectric material and the field plate on the inner wall of the perimeter trenches is connected to a source or trench-gate of the transistor, and wherein the perimeter trenches include dielectric material between the field plates on the inner and outer walls.

2. A transistor as claimed in claim 1, in which each of said perimeter trenches has a field plate on said inner wall.

3. A transistor as claimed in claim 1, in which the field plates are formed of polysilicon.

4. A transistor as claimed in claim 1, in which the transistor cells and perimeter trenches are hexagon cells or square cells.

5. A transistor as claimed in claim 1, in which the inner wall field plate is connected to the trench-gate.

6. A transistor as claimed in claim 1, in which the active area extends beneath a gate bondpad of the transistor.

7. A cellular trench-gate field-effect transistor comprises a semiconductor body having an array of transistor cells, the cells being bounded by a pattern of perimeter trenches lined with dielectric material around the perimeter of the array, the perimeter trenches having an inner wall closer to an active area of the transistor and an outer wall closer to the edge of the transistor, wherein each of said inner and outer walls has a field plate located on the dielectric material and the field plate on the inner wall of the perimeter trenches is connected to a source or trench-gate of the transistor, and wherein the active area extends beneath a gate bondpad of the transistor.