Processor for executing highly efficient VLIW

• US 6,834,336 B2
• Filed: 05/24/2002
• Issued: 12/21/2004
• Est. Priority Date: 06/16/1997
• Status: Expired due to Term

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takayama, Shuichi, Higaki, Nobuo
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US10/155,672
• Publication Number:
  US 20020144084A1
• Time in Patent Office: 942 Days
• Field of Search: 712/210, 712/213, 712/215, 712/24, 712/207, 712/23, 712/219, 712/245, 711/172, 711/165
• US Class Current: 712/24
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/30163 with implied specifier, e.g. top of stack
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3853 of compound instructions

Abstract

A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Claims

1. A VLIW (Very Long Instruction Word) processor comprising:

a fetching unit configured to fetch the instruction block, the instruction block including (a) a format field having a format code and (b) an operation field having a code to be processed by the processor, wherein the format code in the format field indicates whether a code in an operation field of the instruction block should be processed together with a code in the operation field of a succeeding instruction block;

a decoding/judging unit configured to decode the format code of a first instruction block and judge whether to process a first code contained in the operation field of the first instruction block together with a second code contained in the operation field of a second instruction block that succeeds the first instruction block; and

an executing unit configured to process the first and second codes simultaneously when the decoding/judging unit judges positively,

wherein the fetching unit fetches the first instruction block and second instruction block sequentially.

2. The VLIW processor of claim 1, wherein the executing unit is further operable to process the first code and the second code sequentially when the decoding/judging unit judges negatively.

3. The VLIW processor of claim 1, wherein the first and second codes are respective portions of a single code to be processed by the executing unit.

4. The VLIW processor of claim 1, further comprising a holding unit operable to, when the decoding/judging unit judges positively, hold the first code until the first and second codes can be processed together.

5. The VLIW processor of claim 1, wherein:

each instruction block includes a plurality of operation fields,

the format code contained in each instruction block indicating whether a code in one of the plurality of operation fields that is located at a predetermined position should be processed together with a code in operation fields of a succeeding instruction block, and

the first code is the code in the operation field located at the predetermined position.

6. The VLIW processor of claim 1 wherein:

the operation field contains an operation code,

the decoding/judging unit decodes the operation code, and

the executing unit executes an operation corresponding to the decoded operation code.

7. A recording medium recording a plurality of instruction blocks to be fetched by a VLIW (Very Long Instruction Word) processor, each of the instruction blocks including:

a format field having a format code; and

an operation field having a code to be processed by the processor,

wherein the format code in the format field indicates whether a code in an operation field of the instruction block should be processed by the processor together with a code in the operation field of a succeeding instruction block, and

wherein the instruction block and the succeeding instruction block are fetched sequentially.

8. The recording medium of claim 7, wherein the format code in the format field further indicates whether the code in the operation field of the instruction block should be processed by the processor sequentially with a code in the operation field of a succeeding instruction block.

9. The recording medium of claim 7, wherein the plurality of instruction blocks include at least a first instruction block and a second instruction block, wherein a first code contained in an operation field of the first instruction block and a second code contained in an operation field of the second instruction block are respective portions of a single code to be processed by the processor.

10. The recording medium of claim 9, wherein the first code is to be held in a holding unit of the processor until the first and second codes can be processed together.

11. The recording medium of claim 7, wherein:

each instruction block includes a plurality of operation fields,

the format code contained in each instruction block indicating whether a code in one of the plurality of operation fields that is located at a predetermined position should be processed together with a code in operation fields of a succeeding instruction block.

12. The recording medium of claim 7, wherein the operation field contains an operation code indicating an operation to be processed by the processor.

13. An operation executing method for use in a VLIW (Very Long Instruction Word) processor comprising:

a fetching step for fetching the instruction block, each instruction block including (a) a format field having a format code and (b) an operation field having a code to be processed, wherein the format code indicates whether a code in an operation field of the instruction block should be processed together with a code in the operation field of a succeeding instruction block;

a decoding/judging step for decoding the format code of a first instruction block and judging whether to process a first code contained in the operation field of the first instruction block together with a second code contained in the operation field of a second instruction block that succeeds the first instruction block; and

an executing step for (a) processing the first code and the second code sequentially when the decoding/judging step judges negatively and (b) processing the first and second codes together when the decoding/judging step judges positively,

wherein the first instruction block and the second instruction block are fetched sequentially at the fetching step.

14. The method of claim 13, wherein when the decoding/judging step judges positively, the decoding/judging step holds the first code until the first and second codes can be processed together.

15. The method of claim 13, wherein the first and second codes are respective portions of a single code to be processed in the executing step.

16. The method of claim 13, wherein:

each instruction block includes a plurality of operation fields,

the format code contained in each instruction block indicating whether a code in one of the plurality of operation fields that is located at a predetermined position should be processed together with a code in operation fields of a succeeding instruction block, and

the first code is the code in the operation field located at the predetermined position.

17. The method of claim 13, wherein:

the operation field contains an operation code,

the decoding/judging step decodes the operation code, and

the executing step executes an operation corresponding to the decoded operation code.

18. A VLIW (Very Long Instruction Word) processor that executes operations, said processor comprising:

a fetching unit configured to fetch instruction blocks one by one, an instruction block includes a first VLIW instruction, and a second VLIW instruction which, is allocated over a boundary of said instruction block into another instruction block; and

an executing unit configured to execute a VLIW instruction including a plurality of operations executed in parallel, said second VLIW instruction is executed after said first VLIW instruction.

19. The VLIW processor of claim 18, wherein the bit length of said first VLIW instruction and said second VLIW instruction are variable.

20. The VLIW processor of claim 19, wherein each of said instruction blocks includes a format code, wherein said second VLIW instruction is executed after said first VLIW instruction in response to a format code.

21. The VLIW processor of claim 18, wherein said first VLIW instruction and said second VLIW instruction are able to be generated by a compiler.

22. The VLIW processor of claim 21, further comprising:

a cache memory,

wherein said fetching unit fetches said instruction block from an external memory and stores in said cache memory.

23. The VLIW processor of claim 22, further comprising:

a register for holding a code defining said operations.

24. A VLIW (Very Long Instruction Word) processor that executes operations, said processor comprising:

a fetching unit configured to fetch instruction blocks one by one, an instruction block including a first VLIW instruction and a second VLIW instruction, said second VLIW instruction being defined by a code included in at least said instruction block and another instruction block; and

an executing unit configured to execute a VLIW instruction including a plurality of operations executed in parallel, said second VLIW instruction is executed after said first VLIW instruction.

25. The VLIW processor of claim 24, wherein the bit length of said first VLIW instruction and said second VLIW instruction are variable.

26. The VLIW processor of claim 25, wherein each of said instruction blocks includes a format code, wherein said second VLIW instruction is executed after said first VLIW instruction in response to a format code.

27. The VLIW processor of claim 24, wherein said first VLIW instruction and said second VLIW instruction are able to be generated by a compiler.

28. The VLIW processor of claim 27, further comprising:

a cache memory,

wherein said fetching unit fetches said instruction block from an external memory and stores in said cache memory.

29. The VLIW processor of claim 28, further comprising:

a register for holding a code defining said operations.

30. A VLIW (Very Long Instruction Word) processor that executes operations, said processor comprising:

a fetching unit configured to fetch instruction blocks one by one, an instruction block includes a first VLIW instruction and a second VLIW instruction, said second VLIW instruction is included in at least said instruction block and another instruction block; and

an executing unit configured to execute a VLIW instruction including a plurality of operations executed in parallel, said second VLIW instruction is executed after said first VLIW instruction.

31. The VLIW processor of claim 30, wherein the bit length of said first VLIW instruction and said second VLIW instruction are variable.

32. The VLIW processor of claim 31, wherein each of said instruction blocks includes a format code, wherein said second VLIW instruction is executed after said first VLIW instruction in response to said format code.

33. The VLIW processor of claim 30, wherein said first VLIW instruction and said second VLIW instruction are able to be generated by a compiler.

34. The VLIW processor of claim 33, further comprising:

a cache memory,

wherein said fetching unit fetches said instruction block from an external memory and stores in said cache memory.

35. The VLIW processor of claim 34, further comprising:

a register for holding a code defining said operations.