Processor for executing highly efficient VLIW

  • US 6,834,336 B2
  • Filed: 05/24/2002
  • Issued: 12/21/2004
  • Est. Priority Date: 06/16/1997
  • Status: Expired due to Term
First Claim
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1. A VLIW (Very Long Instruction Word) processor comprising:

  • a fetching unit configured to fetch the instruction block, the instruction block including (a) a format field having a format code and (b) an operation field having a code to be processed by the processor, wherein the format code in the format field indicates whether a code in an operation field of the instruction block should be processed together with a code in the operation field of a succeeding instruction block;

    a decoding/judging unit configured to decode the format code of a first instruction block and judge whether to process a first code contained in the operation field of the first instruction block together with a second code contained in the operation field of a second instruction block that succeeds the first instruction block; and

    an executing unit configured to process the first and second codes simultaneously when the decoding/judging unit judges positively, wherein the fetching unit fetches the first instruction block and second instruction block sequentially.

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