Multi-layered gate for a CMOS imager

• US 6,835,637 B2
• Filed: 09/05/2003
• Issued: 12/28/2004
• Est. Priority Date: 06/15/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Linday, Jr., Walter L.
• Application Number:
  US10/654,932
• Publication Number:
  US 20040051123A1
• Time in Patent Office: 480 Days
• Field of Search: 438/69, 438/73, 438/200, 438/585, 438/57, 438/257, 438/579, 438/592
• US Class Current: 438/585
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Claims

1. A method of forming a multi-layered gate for use in an imaging device, comprising the steps of:

providing a semiconductor substrate having a photosensitive region of a first conductivity type;

forming a first insulating layer on the semiconductor substrate and over the photosensitive region;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer over the first conductive layer;

patterning at least the first conductive layer to form a first gate;

forming a third insulating layer over the semiconductor substrate;

forming a second conductive layer over the third insulating layer and at least a portion of the first conductive layer;

forming a second gate from the second conductive layer and the third insulating layer; and

forming a floating diffusion region of a second conductivity type in the substrate adjacent the first gate on a side of the first gate opposite the second gate.

2. The method of claim 1, wherein the first gate is a transfer gate, and the second gate is a photogate.

3. The method of claim 1, wherein the first gate is a photogate, and the second gate is a transfer gate.

4. The method of claim 1, wherein the first gate is a row select gate, and the second gate is a source follower gate.

5. The method of claim 1, wherein the first gate is a source follower gate, and the second gate is a row select gate.

6. The method of claim 1, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

7. The method of claim 1, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

8. The method of claim 1, wherein said step of forming a first insulating layer comprises thermal oxidation.

9. The method of claim 1, wherein said step of forming a first insulating layer comprises deposition.

10. The method of claim 1, wherein said step of forming a second insulating layer comprises deposition.

11. The method of claim 1, wherein said step of forming a first conductive layer comprises chemical vapor deposition.

12. The method of claim 1, wherein said step of forming a second conductive layer comprises chemical vapor deposition.

13. The method of claim 1, wherein the first and the second conductive layers are doped polysilicon layers.

14. The method of claim 1, wherein the first insulating layer is a layer of material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

15. The method of claim 1, wherein the second insulating layer is a layer deposited silicon oxide or silicon oxide hardened by a nitrogen treatment.

16. The method of claim 1, further comprising forming a reset transistor adjacent to the photosensitive region having a doped region of a second conductivity type as a drain, the floating diffusion region being the source of the reset transistor.

17. The method of claim 1, further comprising forming an output transistor having a gate electrically connected to the floating diffusion region.

18. A method of forming a stacked photogate for use in an imaging device, comprising the steps of:

providing a semiconductor substrate having a photosensitive region of a first conductivity type;

forming a first insulating layer on the substrate and over the photosensitive region;

forming a first conductive layer over the first insulating layer adjacent to the photosensitive region;

forming a second insulating layer over the first conductive layer;

patterning the first conductive layer and the second insulating layer to form a transfer gate and a reset gate for a reset transistor;

forming insulating spacers on the sides of the transfer gate;

forming a second conductive layer over the photosensitive region and extending over at least a portion of the transfer gate;

forming a floating diffusion region of a second conductivity type between the transfer gate and the reset gate in the substrate, the floating diffusion region being the source of the reset transistor; and

forming a doped region of a second conductivity type adjacent to the reset gate, the doped region being the drain of the reset transistor.

19. The method of claim 18, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

20. The method of claim 18, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

21. The method of claim 18, wherein said step of forming a first insulating layer comprises thermal oxidation.

22. The method of claim 18, wherein said step of forming a first insulating layer comprises deposition.

23. The method of claim 18, wherein said step of forming a second insulating layer comprises thermal oxidation.

24. The method of claim 18, wherein said step of forming a second insulating layer comprises deposition.

25. The method of claim 18, wherein said step of forming a second insulating layer comprises forming a silicon oxide layer and hardening the silicon oxide layer by a nitrogen treatment.

26. The method of claim 18, wherein said step of forming a first conductive layer comprises chemical vapor deposition.

27. The method of claim 18, wherein said step of forming a second conductive layer comprises chemical vapor deposition.

28. The method of claim 18, wherein the first and the second conductive layers are doped polysilicon layers.

29. The method of claim 18, wherein the first insulating layer is a layer of material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, ON, NO, and ONO.

30. The method of claim 18, further comprising a step of forming a metal silicide layer on the first conductive layer prior to said step of forming a second insulating layer.

31. The method of claim 30, wherein said step of forming a metal silicide layer comprises chemical vapor deposition.

32. The method of claim 30, wherein said step of forming a metal silicide layer further comprises forming a metal layer on the first conductive layer, and annealing the metal layer at a temperature within the range of approximately 300 to 800 degrees Celsius.

33. The method of claim 30, wherein the metal silicide layer is a layer selected from the group consisting of tungsten silicide, titanium silicide, molybdenum silicide, tantalum silicide, platinum silicide, palladium silicide, iridium silicide, and cobalt silicide.

34. The method of claim 18, wherein said step of forming a floating diffusion region comprises ion implantation of at least one dopant into the semiconductor substrate.

35. The method of claim 18, further comprising forming an output transistor having a gate electrically connected to the floating diffusion region.