Synchronizing timing between multiple air link standard signals operating within a communications terminal

• US 6,836,506 B2
• Filed: 08/27/2002
• Issued: 12/28/2004
• Est. Priority Date: 08/27/2002
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, Jon J.
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US10/229,585
• Publication Number:
  US 20040042576A1
• Time in Patent Office: 854 Days
• Field of Search: 375/141, 375/145, 375/354, 375/356, 375/365, 375/367, 370/208, 370/320, 370/335, 370/350, 370/342, 370/441, 370/503, 370/509, 370/514, 370/515
• US Class Current: 375/145
• CPC Class Codes: G01S 19/256 relating to timing, e.g. time of week, code phase, timing offset
• CPC Class Codes: H04B 7/2684 Synchronisation of a mobile station with more than one base station
• CPC Class Codes: H04W 56/004 compensating for timing error of reception due to propagation delay

Abstract

A system and method for synchronizing a number of specialized circuits or application-specific integrated circuits to a common timing standard is provided. The system includes a first communications device including at least first and second type communication paths which is configured to receive first and second timing signals in the first type communications path and to transmit data on the second type communications path. The data is transmitted in association with the received first timing signal. A controller or signal processor element is coupled to the first device and configured to receive the second timing signal and produce a timing word therefrom. A second communications device is coupled to the processor and configured to receive the second timing signal and produce a timing word therefrom. The second communications. device receives the timing word and the transmitted data and derives synchronization information therefrom. The derived synchronization information is related to the first timing signal. The second communications device performs one or more operations in accordance with the received second timing signal and the derived synchronization information.

Claims

1. Apparatus comprising:

a first communications device comprising at least first and second types of communication paths, being configured to receive first and second timing signals in the first type communication path and to transmit data on the second type communication path, the data being transmitted in association with a received first timing signal;

a processor coupled to the first communications device configured to receive the second timing signal and produce a timing word from a second timing signal; and

a second communications device comprising at least the first type communication path, being coupled to the processor and configured to receive the timing word, receive the transmitted data and derive synchronization information therefrom, the synchronization information being related to the first timing signal, and to perform one or more operations in accordance with the received second timing signal and the derived synchronization information.

2. The apparatus of claim 1, wherein the first type communication path comprises a forward link and the second type communication path comprises a reverse link.

3. The apparatus of claim 1, wherein the first and second timing signals respectively comprise a pilot signal and a synchronization channel message signal.

4. The apparatus of claim 1, wherein the first and second communications devices respectively comprise first and second application specific integrated circuits.

5. The apparatus of claim 1, wherein the one or more operations comprise at least deriving timing information associated with the second communications device.

6. The apparatus of claim 1, wherein the received timing word comprises adjustments to compensate for path delays.

7. Apparatus comprising:

a first communications device including at least first and second types of communication paths which are configured to receive first and second timing signals over the first type communication path and transmit data on the second type communication path, the data being transmitted in association with a received first timing signal;

a processor electrically coupled to the first communications device and configured to receive the second timing signal and to produce a timing word from a second timing signal; and

a second communications device including at least the first type communication path, being coupled to the processor and configured to receive the timing word therefrom, to receive the transmitted data and derive synchronization information therefrom, the synchronization information being related to the first timing signal, and to acquire one or more communications signals in accordance with the received second timing signal and the derived synchronization information.

8. The apparatus of claim 7, wherein the first type communication path comprises a forward link and the second type communication path comprises a reverse link.

9. The apparatus of claim 7, wherein the first and second timing signals respectively comprise a pilot signal and a synchronization channel message signal.

10. The apparatus of claim 7, wherein the first and second communications devices respectively comprise first and second application specific integrated circuits.

11. The apparatus of claim 7, wherein the one or more communications signals comprise at least a timing signal associated with a positioning satellite network.

12. The apparatus of claim 7, wherein the received timing word comprises adjustments to compensate for path delays.

13. Apparatus comprising:

a processor;

a tuner coupled to the processor configured to receive a number of radio frequency signals based upon a first processor control signal, the tuner producing a selected frequency signal as an output;

a first switch coupled to the processor having two or more first switch output ports, and being configured to receive a second processor control signal, to receive the selected frequency signal from the tuner, and to selectively switch the received selected frequency signal between the two or more first switch output ports;

a first circuit coupled to the microprocessor, the tuner, and the first switch comprising;

a first receive path having an input port coupled to a first of the two or more first switch output ports, configured to receive the selected frequency signal through the input port, the received selected frequency signal comprising a first type timing component and a synchronization word, the synchronization word being output to the processor, the processor producing a second type timing component in response thereto,

a time tracking device configured to receive the first and second timing components, to perform a first synchronization operation in response to the received first and second timing components, and to produce a synchronization point in accordance with the first synchronization operation,

a code generator coupled to the processor configured to receive a communications message therefrom, and to generate a data sequence in accordance with the communications message and to provide the data sequence to the time tracking device which produces a correlated data sequence based upon the synchronization point and the communications message, and

a first transmit path configured to receive the correlated data sequence and produce a synchronized data stream therefrom, being configured to transmit the synchronized data stream using a first transmit path output port;

a second switch electrically coupled to the processor and to the first transmit path output port, comprising two or more second switch output ports and being configured to receive a third processor control signal, to receive the synchronized data stream, and to selectively switch the received synchronized data stream between the two or more second switch output ports;

a third switch comprising first and second third switch input ports and an output port, wherein the first third switch input port is coupled to the second of the two or more first switch output ports and the second third switch input port is coupled to one of the second switch output ports, the third switch being configured to receive a fourth processor control signal, to receive the selected frequency signal using the first third switch input port, and to receive the synchronized data stream using the second third switch input port;

a second circuit coupled to the processor and the third switch comprising;

a second receive path having an input coupled to the third switch output port being configured to receive a selected one of the synchronized data stream and the selected frequency signal from the input port, and

a correlator coupled to an output of the second receive path and configured to detect the presence of the synchronized data stream when the synchronized data stream is received in the second receive path, the correlator providing, the synchronized data stream as an output; and

a time measurement mechanism having a first input coupled to an output of the correlator and another input coupled to the microprocessor, the time measurement mechanism being configured to receive the synchronized data stream from the correlator, to receive the synchronization word from the processor, and to derive a timing window therefrom.

14. The apparatus of claim 13, wherein the first type timing component comprises pseudorandom noise level timing information.

15. The apparatus of claim 13, wherein the first and second receive paths comprise a forward link.

16. The apparatus of claim 13, wherein the first transmit path comprise a reverse link.

17. A method for acquiring a timing signal in a system including a first communications device including at least first and second type communications path, a second communications device including at least a first type communications path, and a processor, comprising the steps of:

receiving first and second timing signals in the first type communications path of the first communications device;

transmitting data from the second type communications path of the first communications device, the data being transmitted in association with the received first timing signal;

receiving the second timing signal in the processor and converting the second timing signal into a timing word;

receiving in the second communications device (i) the transmitted data and deriving synchronization information therefrom and (ii) the timing word; and

performing one or more operations in accordance with the received transmitted data and the timing word.

18. The method of claim 17, wherein the first and second timing signals respectively comprise a pilot signal and a synchronization channel message.

19. The method of claim 17, wherein the first type communication path comprises a forward link and the second type communication path includes a reverse link.

20. The method of claim 17, wherein the data comprises a synchronization timing word.

21. Apparatus comprising:

a communication device configured to operate in first and second air link modes;

at least first and second type communication paths adapted for facilitating communication with the communication device at least during of the first air link mode;

wherein the communication device is configured to (i) receive first and second timing signals on the first type communication path, first and second timing signal data respectively representative of the first and second timing signals being stored in a communication device memory, and (ii) transmit communication data on the second type communication path, the communication data being transmitted in accordance with the first timing signal data;

wherein the second air link mode includes at least a first type communication path configured for facilitating communication with the communication device during operation of the second air link mode;

wherein the first type communication path of the second air link mode is configured to receive the transmitted communication data and produce first type synchronization information therefrom;

a timing mechanism configured for activation during the second air link mode and to receive the first type synchronization information; and

a processor coupled to the communication device and configured to receive the second timing signal data stored in the memory and produce second type synchronization information therefrom, the processor providing the second type synchronization information to the timing mechanism during the activation.

22. The apparatus of claim 21, wherein the first and second air link modes comprise compatibility with at least one of a satellite, CDMA, W-CDMA, and GSM based wireless communication system.