CMOS image sensor arrangement with reduced pixel light shadowing

  • US 6,838,715 B1
  • Filed: 04/29/2003
  • Issued: 01/04/2005
  • Est. Priority Date: 04/30/2002
  • Status: Active Grant
First Claim
Patent Images

1. A CMOS image sensor comprising:

  • a plurality of pixels arranged in an array;

    said plurality of pixels including a first pixel proximate an optical center of said array, and a second pixel proximate a peripheral edge of said array;

    a first metal interconnect segment associated with said first pixel; and

    a second metal interconnect segment associated with said second pixel, wherein said first metal interconnect segment and second metal interconnect segment are situated in a first metal layer, wherein said second metal interconnect segment is shifted closer to said optical center than said first metal interconnect segment so that said second metal interconnect segment approximately aligns with a principal ray angle incident said second pixel.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×