Metal oxide semiconductor field effect transistors (MOSFETS) used in ink-jet head chips and method for making the same

• US 6,841,830 B2
• Filed: 07/28/2003
• Issued: 01/11/2005
• Est. Priority Date: 12/31/2002
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chen, Chun-Jung, Liou, Jian-Chiun, Liu, Chien-Hung, Hu, Je-Ping
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/627,637
• Publication Number:
  US 20040124449A1
• Time in Patent Office: 533 Days
• Field of Search: 257/368, 257/327, 257/650, 257/751, 257382-384, 347 57- 59, 347/61
• US Class Current: 257/368
• CPC Class Codes: B41J 2/14129 Layer structure
• CPC Class Codes: B41J 2002/14387 Front shooter
• CPC Class Codes: B41J 2202/13 Heads having an integrated circuit
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A MOSFET and the method for fabricating them are disclosed to make the inkjet head chips. The MOSFET has the scaled-down junction formation for the source and drain. Using a lower temperature process and interlayer dielectric, the source and drain dopants can not be diffused deeply due to high-temperature driver-in. The contact holes of the drain are provided with plugs of refractory material to avoid spiking between the metal and silicon. This achieves the requirement of high-density devices on the print head chip.

Claims

1. A metal oxide semiconductor field effect transistor (MOSFET) used in ink-jet head chips, which is connected to an inkjet actuator for controlling the electrical voltage or current passing through the inkjet actuator;

the MOSFET comprising at least a source, a drain, and a gate and being characterized in that;

the MOSFET is covered with a borophosphosilicate glass (BPSG);

at least one contact hole through the BPSG is filled with a plug material at the position corresponding to the drain;

the gate length is between 0.35 μ

m and 3.5 μ

m, and the sum of junction depths at the source and the drain is 0.2 to 0.75 times that of the gate length.

2. The metal oxide semiconductor field effect transistor of claim 1, wherein the BPSG has a thickness between 150 nm and 1000 nm.

3. The metal oxide semiconductor field effect transistor of claim 1, wherein the BPSG has a boron content between 0.5 wt % and 6.0 wt %.

4. The metal oxide semiconductor field effect transistor of claim 1, wherein the BPSG has a reflow temperature between 850°

C. and 925°

C.

5. The metal oxide semiconductor field effect transistor of claim 1, wherein the plug material has a thickness between 0.01 μ

m and 1.0 μ

m.

6. The metal oxide semiconductor field effect transistor of claim 1, wherein the plug material is one selected from the group consisting of W, Pt, Ti, Co, Ni, Mo, Ta, Si, and their alloys and compounds.

7. A chip structure of an integrated-driver ink-jet head, comprising:

a plurality of MOSFETs, which contains at least one gate, a source, and a drain, wherein the MOSFET is covered with a borophosphosilicate glass (BPSG);

at least one contact hole through the BPSG is filled with a plug material at the position corresponding to the drain;

the gate length is between 0.35 μ

m and 3.51 μ

m, and the sum of junction depths at the source and the drain is 0.2 to 0.75 times that of the gate length;

a plurality of actuators, which are in electrical communications with the MOSFETs for providing the energy to eject fluid out; and

a plurality of fluid-flow structures, which define at least one fluid-flow channel on an fluid-chamber and a nozzle for the fluid to refill and are in communications with said actuators to eject fluid out.

8. The chip structure of claim 7, wherein the BPSG has a thickness between 150 nm and 1000 nm.

9. The chip structure of claim 7, wherein the BPSG has a boron content between 0.5 wt % and 6.0 wt %.

10. The chip structure of claim 7, wherein the BPSG has a reflow temperature between 850°

C. and 925°

C.

11. The chip structure of claim 7, wherein the plug material has a thickness between 0.1 μ

m and 1.0 μ

m.

12. The chip structure of claim 7, wherein the plug material is at least one selected from the group consisting of W, Pt, Ti, Co, Ni, Mo, Ta, Si, and their alloys and compounds.