Multi-dice chip scale semiconductor components and wafer level methods of fabrication

• US 6,841,883 B1
• Filed: 03/31/2003
• Issued: 01/11/2005
• Est. Priority Date: 03/31/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Wark, James M., Hembree, David R., Kirby, Kyle K., Benson, Pete A., Farnworth, Warren M., Wood, Alan G., Hiatt, William M.
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US10/403,937
• Publication Number:
  US 20040256734A1
• Time in Patent Office: 652 Days
• Field of Search: 257/777, 257/774, 257/618, 257/686
• US Class Current: 257/777
• CPC Class Codes: B33Y 70/00 Materials specially adapted for additive manufacturing
• CPC Class Codes: B33Y 80/00 Products made by additive manufacturing
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05118 Zinc [Zn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05178 Iridium [Ir] as principal constituent
• CPC Class Codes: H01L 2224/0518 : Molybdenum [Mo] as principal constituent
• CPC Class Codes: H01L 2224/05181 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05559 : non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05569 : the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 : the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13005 : Structure
• CPC Class Codes: H01L 2224/13006 : Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13009 : Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.

Claims

1. A semiconductor component comprising:

a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate;

a thinned secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias; and

a plurality of terminal contacts on the base die in electrical communication with the conductive vias.

2. A semiconductor component comprising:

a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate;

a secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias;

a plurality of terminal contacts on the base die in electrical communication with the conductive vias; and

an encapsulant on the back side at least partially encapsulating the secondary die.

3. A semiconductor component comprising:

a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate;

a secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias;

a plurality of terminal contacts on the base die in electrical communication with the conductive vias; and

a polymer layer on the base die configured as a protective member, a rigidifying member and a stencil for forming the terminal contacts.

4. The semiconductor component of claim 3 further comprising a second secondary die bonded to the secondary die.

5. A semiconductor component comprising:

a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate;

a secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias; and

a plurality of terminal contacts on the base die in electrical communication with the conductive vias;

the base die and the secondary die comprising thinned dice.

6. The semiconductor component of claim 5 wherein the conductive vias comprise openings in the substrate at least partially filled with a conductive material.

7. A semiconductor component comprising:

a thinned base die comprising a circuit side, a back side, a plurality of conductive vias and a plurality of contacts on the back side in electrical communication with the conductive vias;

a thinned secondary die stacked on the base die and bonded to the contacts; and

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias.

8. The semiconductor component of claim 7 further comprising an encapsulant on the back side at least partially encapsulating the secondary die.

9. The semiconductor component of claim 7 further comprising a cap plate bonded to the secondary die comprising a plurality of conductors configured to electrically connect selected base die contacts to selected secondary die contacts.

10. The semiconductor component of claim 7 further comprising a cap plate bonded to the secondary die and a plurality of electrical components on the cap plate in electrical communication with the secondary die.

11. The semiconductor component of claim 7 wherein the contacts comprise bumps in physical contact with the conductive vias.

12. The semiconductor component of claim 7 wherein a peripheral outline of the base die matches that of the component.

13. The semiconductor component of claim 7 wherein the conductive vias comprise a metal and a solder alloy.

14. A semiconductor component comprising:

a base die comprising a thinned semiconductor substrate and a plurality of conductors on the substrate;

an internal signal transmission system comprising a plurality of conductive vias in the substrate in electrical communication with the conductors, and a plurality of contacts on the conductive vias;

a secondary die bonded to the contacts; and

a plurality of terminal contacts on the conductors.

15. The semiconductor component of claim 14 wherein the secondary die comprises a plurality of metal bumps bonded to the contacts.

16. The semiconductor component of claim 14 wherein the conductors comprise redistribution conductors on a circuit side of the base die.

17. The semiconductor component of claim 14 further comprising a cap plate bonded to the secondary die and a plurality of electrical components on the cap plate in electrical communication with the secondary die.

18. The semiconductor component of claim 14 further comprising a cap plate bonded to the secondary die configured to short selected contacts on the base die to selected contacts on the secondary die.

19. The semiconductor component of claim 14 further comprising an electrically conductive polymer bonding the secondary die to the contacts.

20. The semiconductor component of claim 14 further comprising a module substrate bonded to the base die.

21. The semiconductor component of claim 14 wherein the secondary die and the substrate have a thickness of about 100 μ

m to 600 μ

m.

22. The semiconductor component of claim 14 wherein the conductive vias comprise openings in the substrate at least partially filled with a material selected from the group consisting of metal, solder, conductive polymers and nano-particle conductive polymers.

23. A semiconductor component comprising:

a base die comprising a thinned semiconductor substrate having a peripheral outline, a circuit side, a back side, and a plurality of conductive vias in the substrate;

a thinned secondary die bonded to the back side and comprising a plurality of integrated circuits in electrical communication with the conductive vias;

an encapsulant on the back side having the peripheral outline and at least partially encapsulating the secondary die;

a polymer layer on the circuit side having the peripheral outline and configured as a protective and rigidifying member for the component; and

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias.

24. The semiconductor component of claim 23 wherein the polymer layer is configured as a stencil for forming the terminal contacts.

25. The semiconductor component of claim 23 wherein the secondary die comprises a plurality of bumped contacts bonded to the conductive vias.

26. The semiconductor component of claim 23 wherein the base die comprises a plurality of bumped contacts on the conductive vias bonded to the secondary die.

27. A semiconductor component comprising:

a base die comprising a thinned semiconductor substrate having a peripheral outline, a circuit side, a back side, and a plurality of conductive vias in the substrate;

a thinned secondary die bonded to the back side and comprising a plurality of integrated circuits in electrical communication with the conductive vias;

an encapsulant on the back side having the peripheral outline and at least partially encapsulating the secondary die;

a polymer layer on the circuit side having the peripheral outline and configured as a protective and rigidifying member for the component;

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias; and

a second secondary die bonded to the thinned secondary die in electrical communication with the conductive vias.

28. A semiconductor component comprising:

a first base die comprising a plurality of first conductive vias;

a second base die stacked and bonded to the first base die comprising a plurality of second conductive vias in electrical communication with the first conductive vias;

a secondary die stacked and bonded to the second base die comprising a plurality of bumped contacts bonded to the second conductive vias; and

a plurality of terminal contacts on the first base die in electrical communication with the first conductive vias,

with either the first base die, the second base die or the secondary die comprising a thinned die.

29. The semiconductor component of claim 28 wherein the terminal contacts comprise balls or bumps in a grid array.

30. The semiconductor component of claim 28 further comprising an underfill layer between the first base die and the secondary die.

31. The semiconductor component of claim 28 wherein the first base die, the second base die and the secondary die comprise known good dice.

32. The semiconductor component of claim 28 wherein the secondary die comprises a cap plate having a plurality of electrical components thereon.

33. The semiconductor component of claim 28 wherein the first conductive vias and the second conductive vias comprise a material selected from the group consisting of metal, solder, conductive polymers and nano-particle conductive polymers.

34. The semiconductor component of claim 28 wherein the bumped contacts comprise metal bumps in physical contact with the conductive vias.

35. A semiconductor component comprising:

a base die comprising a semiconductor substrate having a circuit side and a back side, a plurality of die contacts on the circuit side, a plurality of conductive vias in the substrate in electrical communication with the die contacts, a plurality of redistribution conductors on the circuit side in electrical communication with the conductive vias, and a plurality of terminal contacts on the circuit side in electrical communication with the conductors;

a secondary die bonded to the back side;

an underfill layer bonding the secondary die to the base die; and

a plurality of bumped contacts bonded to the conductive vias and to the secondary die.

36. The semiconductor component of claim 35 further comprising a polymer layer on the circuit side configured as a rigidifying member, a protective member, and a stencil for forming the terminal contacts.

37. The semiconductor component of claim 35 further comprising a module substrate bonded to the base die.

38. The semiconductor component of claim 35 further comprising an encapsulant on the back side at least partially encapsulating the secondary die.

39. The semiconductor component of claim 35 further comprising an electrically insulating polymer layer in the conductive vias and on the back side.

40. The semiconductor component of claim 35 wherein the base die and the secondary die comprise thinned dice.

41. The semiconductor component of claim 35 wherein the terminal contacts comprise bumps, balls or pins in a grid array.

42. The semiconductor component of claim 35 wherein the conductive vias comprise lasered openings and a conductive material in the openings, and the bumped contacts comprise solder bumps bonded to the conductive material.

43. The semiconductor component of claim 35 wherein the base die and the component have a same peripheral outline.

44. The semiconductor component of claim 35 wherein the conductive vias comprise openings in the substrate, an insulating layer on the openings, and a conductive material in the openings.

49. The semiconductor component of claim 44 wherein the second secondary die includes a plurality of electrical components thereon in electrical communication with the secondary contacts.

50. The semiconductor component of claim 44 wherein the contacts comprise bumps in physical contact with the conductive vias.

45. A semiconductor component comprising:

a base die comprising a circuit side, a back side, a plurality of conductive vias and a plurality of contacts on the back side in electrical communication with the conductive vias;

a first secondary die stacked on the base die and bonded to the contacts, the first secondary die comprising a plurality of secondary conductive vias and a plurality of secondary contacts in electrical communication with the secondary conductive vias;

a second secondary die stacked on the first secondary die and bonded to the secondary contacts;

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias; and

a polymer layer on the circuit side configured as a stencil for the terminal contacts.

46. A semiconductor component comprising:

a base die comprising a circuit side, a back side, a plurality of conductive vias and a plurality of contacts on the back side in electrical communication with the conductive vias;

a first secondary die stacked on the base die and bonded to the contacts, the first secondary die comprising a plurality of secondary conductive vias and a plurality of secondary contacts in electrical communication with the secondary conductive vias;

a second secondary die stacked on the first secondary die and bonded to the secondary contacts;

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias; and

an encapsulant on the back side at least partially encapsulating the first secondary die and the second secondary die.

47. A semiconductor component comprising:

a base die comprising a circuit side, a back side, a plurality of conductive vias and a plurality of contacts on the back side in electrical communication with the conductive vias;

a first secondary die stacked on the base die and bonded to the contacts, the first secondary die comprising a plurality of secondary conductive vias and a plurality of secondary contacts in electrical communication with the secondary conductive vias;

a second secondary die stacked on the first secondary die and bonded to the secondary contacts;

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias; and

a polymer layer on the circuit side configured as a rigidifying member, a protective member, and a stencil for forming the terminal contacts.

48. A semiconductor component comprising:

a base die comprising a circuit side, a back side, a plurality of conductive vias and a plurality of contacts on the back side in electrical communication with the conductive vias;

a first secondary die stacked on the base die and bonded to the contacts, the first secondary die comprising a plurality of secondary conductive vias and a plurality of secondary contacts in electrical communication with the secondary conductive vias;

a second secondary die stacked on the first secondary die and bonded to the secondary contacts; and

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias;

the base die, the first secondary die and the second secondary die comprising thinned dice.

51. A system comprising:

a substrate; and

a semiconductor component on the substrate comprising a base die comprising a thinned substrate having a back side, and a plurality of conductive vias in the substrate, a thinned secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias, and a plurality of terminal contacts on the base die in electrical communication with the conductive vias.

52. A system comprising:

a substrate;

a semiconductor component on the substrate comprising a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate, a secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias, and a plurality of terminal contacts on the base die in electrical communication with the conductive vias; and

a cap plate bonded to the secondary die configured to short selected contacts on the base die to selected contacts on the secondary die.

53. A system comprising:

a substrate; and

a semiconductor component on the substrate comprising a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate, a secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias, and a plurality of terminal contacts on the base die in electrical communication with the conductive vias; and

a cap plate bonded to the secondary die and at least one electrical element on the cap plate in electrical communication with the secondary die.

54. The system of claim 53 wherein the substrate is contained in a device selected from the group consisting of a module, a package, a computer, a camcorder, a camera, a cell phone, and a medical device.

55. A system comprising:

a substrate;

a semiconductor component on the substrate comprising a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate, a secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias, and a plurality of terminal contacts on the base die in electrical communication with the conductive vias; and

an encapsulant on the back side at least partially encapsulating the secondary die.

56. A system comprising:

a substrate;

a semiconductor component on the substrate comprising a base die comprising a substrate having a back side, and a plurality of conductive vias in the substrate, a secondary die having a circuit side bonded to the back side and a plurality of contacts bonded to the conductive vias, and a plurality of terminal contacts on the base die in electrical communication with the conductive vias; and

a polymer layer on the base die configured as a protective member, a rigidifying member and a stencil for forming the terminal contacts.

57. A system comprising:

a substrate comprising a plurality of electrodes; and

a semiconductor component on the substrate comprising;

a thinned base die comprising a circuit side, a back side, a plurality of conductive vias and a plurality of contacts on the back side in electrical communication with the conductive vias;

a thinned secondary die stacked on the base die and bonded to the contacts; and

a plurality of terminal contacts on the circuit side in electrical communication with the conductive vias and bonded to the electrodes.

58. The system of claim 57 further comprising a second secondary die stacked on and bonded to the secondary die.

59. The system of claim 57 further comprising a cap plate stacked on and bonded to the secondary die.

60. The system of claim 57 wherein the system comprises a multi chip module, a system in a package, a computer, a camcorder, a camera, a cell phone, or a medical device.

61. A system comprising:

a substrate comprising a plurality of electrodes;

a semiconductor component on the substrate comprising;

a base die comprising a thinned substrate having a peripheral outline and a plurality of conductive vias in the substrate;

a thinned secondary die comprising a plurality of bumped contacts bonded to the conductive vias and electrically connecting the base die and the secondary die;

an encapsulant on the base die having the peripheral outline and at least partially encapsulating the secondary die;

a rigidifying polymer layer on the base die having the peripheral outline; and

a plurality of terminal contacts on the base die proximate to the polymer layer in electrical communication with the conductive vias and bonded to the electrodes.

62. The system of claim 61 wherein the substrate comprises a module substrate or a package substrate.

63. The system of claim 61 wherein the conductive vias comprise a material selected from the group consisting of metal, solder, conductive polymers and nano particle conductive polymers.

64. The system of claim 61 further comprising a plurality of components on the substrate substantially identical to the component.

65. The system of claim 61 wherein the polymer layer comprises a stencil for forming the terminal contacts.

66. The system of claim 61 wherein the conductive vias comprise openings in the substrate, an insulating layer on the openings, and a conductive material in the openings.

67. The system of claim 61 further comprising a second secondary die stacked on and bonded to the secondary die.

68. The system of claim 61 further comprising a cap plate stacked on and bonded to the secondary die.

69. The system of claim 61 further comprising a cap plate stacked on and bonded to the secondary die and configured to short selected contacts on the base die to selected contacts on the secondary die.

70. The system of claim 61 further comprising a cap plate stacked on and bonded to the secondary die and a plurality of electrical components on the cap plate in electrical communication with the secondary die.

71. The system of claim 61 wherein the system comprises a multi chip module, a system in a package, a computer, a camcorder, a camera, a cell phone, or a medical device.