Drive circuit

• US 6,844,769 B2
• Filed: 02/14/2003
• Issued: 01/18/2005
• Est. Priority Date: 02/20/2002
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamamoto, Yasunori, Iwanaga, Taishi
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US10/366,524
• Publication Number:
  US 20030155958A1
• Time in Patent Office: 704 Days
• Field of Search: 327/108, 327/112, 327/379, 327/389, 327/391, 327/333, 327/427, 327/390, 327/434, 327/437, 326/68, 326 80- 83
• US Class Current: 327/333
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

The amplitude expansion circuit as a main part of a drive circuit includes: a VM DC power supply line to which a voltage VM is applied; a VH DC power supply line to which a voltage VH roughly twice as high as the voltage VM is applied; an inverter circuit receiving a pulse signal oscillating between the ground voltage and the voltage VM; another inverter circuit receiving a pulse signal oscillating between the voltage VM and the voltage VH in correspondence with the oscillation of the voltage level of the above pulse signal; a p-channel MOSFET having a gate receiving an output from the inverter circuit; another p-channel MOSFET having a gate connected to the VM DC power supply line; an n-channel MOSFET having a gate connected to the VM DC power supply line; and another n-channel MOSFET having a gate receiving an output from the other inverter circuit. A common connection node of the p-channel MOSFET and the n-channel MOSFET works as the output terminal of the amplitude expansion circuit.

Claims

1. An amplitude expansion circuit comprising:

a first DC power supply line to which a first potential is applied;

a second DC power supply line to which a second potential is applied;

an intermediate power supply line to which an intermediate potential between the first potential and the second potential is applied;

a first inverter circuit receiving a first pulse signal changing between the first potential and the intermediate potential, the first inverter circuit operating with power supplies from the first DC power supply line and the intermediate power supply line;

a second inverter circuit receiving a second pulse signal outputted from a level shift circuit, the second pulse signal changing between the second potential and the intermediate potential, the second inverter circuit operating with power supplies from the second DC power supply line and the intermediate power supply line;

a first MOSFET of one conductivity connected between the second DC power supply line and the first DC power supply line, a gate of the first MOSFET receiving an output signal from the second inverter circuit;

a second MOSFET of the one conductivity connected between the first MOSFET and the first DC power supply line, a gate of the second MOSFET being connected to the intermediate power supply line;

a third MOSFET of the other conductivity connected between the second MOSFET and the first DC power supply line, a gate of the third MOSFET receiving an output signal from the first inverter circuit; and

a fourth MOSFET of the other conductivity connected between the second MOSFET and the third MOSFET, a gate of the fourth MOSFET being connected to the

a fifth MOSFET of the other conductivity connected between a common connection node of the first MOSFET and the second MOSFET and the intermediate power supply line, a gate of the fifth MOSFET being connected to the second DC power supply line; and

a sixth MOSFET of the one conductivity connected between a common connection node of the third MOSFET and the fourth MOSFET and the intermediate power supply line, a gate of the sixth MOSFET being connected to the first DC power supply line.

wherein a common connection node of the second MOSFET and the forth MOSFET is an output terminal of the amplitude expansion circuit.

2. The amplitude expansion circuit of claim 1, further comprising a seventh MOSFET of the other conductivity connected between the second inverter circuit and the intermediate power supply line, a source, a drain and a gate of the seventh MOSFET being connected to a low-potential side power supply node of the second inverter circuit, the intermediate power supply line, and the second DC power supply line, respectively.

3. The amplitude expansion circuit of claim 1, further comprising an eighth MOSFET of the other conductivity connected between the fifth MOSFET and the intermediate power supply line, a source, a drain and a gate of the eighth MOSFET being connected to a source of the fifth MOSFET, the intermediate power supply line, and the second DC power supply line, respectively.

4. A predrive circuit comprising:

the amplitude expansion circuit;

level shift circuit;

the first DC power supply line;

the second DC power supply line;

an intermediate power supply line to which an intermediate potential between the first potential and the second potential is applied;

wherein the amplitude expansion circuit includes;

a first inverter circuit receiving a first pulse signal changing between the first potential and the intermediate potential, the first inverter circuit operating with power supplies from the first DC power supply line and the intermediate power supply line;

a second inverter circuit receiving a second pulse signal outputted from a level shift circuit, the second pulse signal changing between the second potential and the intermediate potential, the second inverter circuit operating with power supplies from the second DC power supply line and the intermediate power supply line;

a first MOSFET of one conductivity connected between the second DC power supply line and the first DC power supply line, a gate of the first MOSFET receiving an output signal from the second inverter circuit;

a second MOSFET of the one conductivity connected between the first MOSFET and the first DC power supply line, a gate of the second MOSFET being connected to the intermediate power supply line;

a third MOSFET of the other conductivity connected between the second MOSFET and the first DC power supply line, a gate of the third MOSFET receiving an output signal from the first inverter circuit; and

a fourth MOSFET of the other conductivity connected between the second MOSFET and the third MOSFET, a gate of the fourth MOSFET being connected to the intermediate power supply line,

wherein a common connection node of the second MOSFET and the fourth MOSFET is an output terminal of the amplitude expansion circuit,

wherein the level shift circuit includes;

a third inverter circuit operating with power supplies from the first DC power supply line and the intermediate power supply line;

a fourth inverter circuit operating with power supplies from the second DC power supply line and the intermediate power supply line;

a first diode having an anode connected to the intermediate power supply line and a cathode connected to an input node of the fourth inverter circuit; and

a capacitor connected between an output node of the third inverter circuit and the input node of the fourth inverter circuit,

wherein an output of the fourth inverter circuit is input into the second inverter circuit.

5. The predrive circuit of claim 4, wherein the level shift circuit further comprises:

a ninth MOSFET of the other conductivity connected between the fourth inverter circuit and the intermediate power supply line, a source, a drain and a gate of the ninth MOSFET being connected to a low-potential side power supply node of the fourth inverter circuit, the intermediate power supply line, and the second DC power supply line, respectively; and

a tenth MOSFET of the other conductivity connected between the anode of the first diode and the intermediate power supply line, a source, a drain and a gate of the tenth MOSFET being connected to the anode of the first diode, the intermediate power supply line, and the second DC power supply line, respectively.

6. The predrive circuit of claim 4 or 5, wherein the level shift circuit further comprises:

an eleventh MOSFET connected between the intermediate power supply line and the input node of the fourth inverter circuit, a gate of the eleventh MOSFET being connected to the second DC power supply line.

7. The predrive circuit of claim 4 or 5, wherein the level shift circuit further comprises:

a twelfth MOSFET connected between the second DC power supply line and the input node of the fourth inverter circuit, a gate of the twelfth MOSFET being connected to the intermediate power supply line.

8. A drive circuit comprising:

an amplitude expansion circuit;

a push-pull circuit;

a first DC power supply line to which a first potential is applied;

a second DC power supply line to which a second potential is applied; and

an intermediate power supply line to which an intermediate potential between the first potential and the second potential is applied;

wherein the amplitude expansion circuit includes;

a first inverter circuit receiving a first pulse signal changing between the first potential and the intermediate potential, the first inverter circuit operating with power supplies from the first DC power supply line and the intermediate power supply line;

a second inverter circuit receiving a second pulse signal outputted from a level shift circuit, the second pulse signal changing between the second potential and the intermediate potential, the second inverter circuit operating with power supplies from the second DC power supply line and the intermediate power supply line;

a first MOSFET of one conductivity connected between the second DC power supply line and the first DC power supply line, a gate of the first MOSFET receiving an output signal from the second inverter circuit;

a second MOSFET of the one conductivity connected between the first MOSFET and the first DC power supply line, a gate of the second MOSFET being connected to the intermediate power supply line;

a third MOSFET of the other conductivity connected between the second MOSFET and the first DC power supply line, a gate of the third MOSFET receiving an output signal from the first inverter circuit; and

a fourth MOSFET of the other conductivity connected between the second MOSFET and the third MOSFET, a gate of the fourth MOSFET being connected to the intermediate power supply line,

a fifth MOSFET of the other conductivity connected between a common connection node of the first MOSFET and the second MOSFET and the intermediate power supply line, a gate of the fifth MOSFET being connected to the second DC power supply line; and

a sixth MOSFET of the one conductivity connected between a common connection node of the third MOSFET and the fourth MOSFET and the intermediate power supply line, a gate of the sixth MOSFET being connected to the first DC power supply line,

wherein a common connection node of the second MOSFET and the fourth MOSFET is an output terminal of the amplitude expansion circuit,

wherein the push-pull circuit includes;

a first power switching element connected between a predetermined power supply line and the first DC power supply line, a gate of the first power switching element receiving an output signal from the output terminal of the amplitude expansion circuit; and

a second power switching element connected between the first power switching element and the first DC power supply line,

wherein a common connection node of the first power switching element and the second power switching element is an output terminal of the drive circuit.