Latched row logic for a rolling exposure snap
First Claim
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1. A system for controlling a pixel sensor, the system comprising:
- an array of pixel sensors, each pixel sensor configured to obtain light, and convert said light to an electrical signal indicative thereof, said array arranged in functional blocks which are made up of rows; and
a readout control system for said array, said readout control system including a controller which first controls a desired functional block to begin integrating at a first time, later, at a time after said first time, controls said functional block to readout information therefrom, said controller including a latched control part which at a first time is set to hold a selected functional block in an integrating mode and at a second time is reset to hold said functional block in a reset mode, wherein each of said pixel sensors are active pixel sensors having a CMOS image sensor, and an in-pixel buffer transistor and an in-pixel select transistor, and wherein said readout control system reads out said information by enabling said select transistors for a selected block and wherein said readout control system further comprises a row decoder, wherein said row decoder comprises a set/reset type latch, driven by a first set signal and second set signal, said first set signal comprising a combined signal for global reset or individual reset and said second set signal comprising a combined signal from a global set and an individual set.
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Abstract
A rolling electronic snap enables each row to integrate for a defined period of time. A control system for the rolling electronic snap includes a latched row logic which latches into reset. The device can be removed from reset in order to integrate. After integrating, the row is selected to receive the information therefrom and then the reset is again maintained. By latching the row in and out of reset, its state can be maintained for longer periods of time.
59 Citations
11 Claims
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1. A system for controlling a pixel sensor, the system comprising:
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an array of pixel sensors, each pixel sensor configured to obtain light, and convert said light to an electrical signal indicative thereof, said array arranged in functional blocks which are made up of rows; and
a readout control system for said array, said readout control system including a controller which first controls a desired functional block to begin integrating at a first time, later, at a time after said first time, controls said functional block to readout information therefrom, said controller including a latched control part which at a first time is set to hold a selected functional block in an integrating mode and at a second time is reset to hold said functional block in a reset mode, wherein each of said pixel sensors are active pixel sensors having a CMOS image sensor, and an in-pixel buffer transistor and an in-pixel select transistor, and wherein said readout control system reads out said information by enabling said select transistors for a selected block and wherein said readout control system further comprises a row decoder, wherein said row decoder comprises a set/reset type latch, driven by a first set signal and second set signal, said first set signal comprising a combined signal for global reset or individual reset and said second set signal comprising a combined signal from a global set and an individual set. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A row logic latch control apparatus for controlling readout of an array of pixel sensors comprising:
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a set/reset type latch;
a first signal block connected to said set/reset type latch wherein said first signal block provides a set/reset signal to said set/reset type latch when a predetermined logical relationship exists between a row decoder output signal, an individual reset signal and a global reset signal; and
a second signal block connected to said set/reset type latch wherein said second signal block provides a clear signal to said set/reset type latch when a predetermined relationship logical exists between said row decoder output signal, an individual clear signal and a global clear signal.
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Specification
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Current AssigneeAptina Imaging Corporation (ON Semiconductor Corporation)
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Original AssigneeMicron Technology, Inc.
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InventorsFossum, Erie R.
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Primary Examiner(s)Christensen, Andrew
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Assistant Examiner(s)TRAN, NHAN T
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Application NumberUS09/281,361Time in Patent Office2,128 DaysField of Search348294-297, 348302-308, 348/221.1, 348/220.1, 348/362, 348311-324, 257291-293, 250/208.1US Class Current348/296CPC Class CodesH04N 25/531 by controlling rolling shut...H04N 25/76 Addressed sensors, e.g. MOS...
