Increasing readout speed in CMOS APS sensors through block readout

• US 6,847,399 B1
• Filed: 03/23/1999
• Issued: 01/25/2005
• Est. Priority Date: 03/23/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ang, Lin-Ping
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Tillery, Rashawn N.
• Application Number:
  US09/274,739
• Time in Patent Office: 2,135 Days
• Field of Search: 348/302, 348/304, 348/307, 348/308, 348/241, 348/246, 348/294, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines. Block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.

Claims

1. An image sensor comprising:

a shared block readout line;

m blocks, wherein m is a positive integer greater than one and each one of said m blocks comprises;

k column readout circuits, each of said k column read out circuits for reading out a respective activated image sensor element, said k column readout circuit being commonly coupled to at least one shared block readout line, where k is a positive integer greater than one; and

m block select switches, wherein each block select switch selectively couples the k column readout circuits of one of said blocks to said shared block readout line.

2. The image sensor of claim 1, wherein said image sensor elements are arranged as a plurality of rows in a pixel array, and for each of said blocks, the column readout circuits read out image sensor elements of an activated row.

3. The image sensor of claim 2, wherein each column readout circuit comprises a column select transistor.

4. The image sensor of claim 2, wherein the relationship between k and m is represented by the equation k=m^1/2.

5. The image sensor of claim 3, wherein said image sensor comprises a linear array of image sensing elements.

6. The image sensor of claim 3, wherein said image sensor comprises a non-linear array of image sensing elements.

7. The image sensor of claim 2, further comprising at least a first set of super-block select switches arranged in cascade fashion relative to said block select switches to further reduce the parasitic capacitance effects from non-driven signal readout lines.

8. The image sensor of claim 2, wherein said image sensor elements are active pixel sensors, having a CMOS photo sensor, and at least one transistor for buffering, within each pixel.

9. An image sensor, comprising:

a shared readout line;

a plurality of readout circuits, said plurality of readout circuit organized into a plurality of blocks, each of said blocks including at least two of said readout circuits, and each of said readout circuits being associated with said shared readout line;

a plurality of block select switches, for selecting an associated one of said plurality of blocks;

wherein each of the block select switches

is enabled only when a pixel signal corresponding to one of said readout circuits in the associated block is to be read out to couple every readout circuit in said associated block to said shared readout line, and

is disabled when no pixel signal corresponding to any of said readout circuits in the associated block is to be read out, to decouple every readout circuit in said associated block from said shared readout line.

10. The image sensor of claim 9, further comprising at least a first set of super-block select switches arranged in cascade fashion relative to said block select switches to further reduce the parasitic capacitance effects from non-driven signal readout lines.

11. The image sensor of claim 9, wherein each block readout circuit is associated with a column of the image sensor array, and comprises a column select transistor.

12. The image sensor of claim 9, wherein

there are m blocks, where m is a positive integer greater than one,

each of said m blocks include k readout circuits, where k is a positive integer greater than one, and

a relationship between m and k is expressed by the equation k=m^1/2.

23. The image sensor of claim 9, wherein said readout circuits are active pixels, with a CMOS photo sensor, and an in-pixel buffer transistor.

13. An image sensor device, comprising:

a plurality of signal readout lines, said plurality of signal readout lines arranged in a plurality of blocks, wherein each block includes at least two of said plurality of signal readout lines;

a shared readout line;

a plurality of block select switches, for selecting an associated one of said plurality of blocks;

wherein each of the block select switches

is enabled only when a signal driven on one of said signal readout lines in the associated block is to be read out to couple every signal readout line in the associated block to said shared readout line, and

is disabled when there is no signal from any of said signal readout lines in the associated block is to be read out.

14. The device of claim 13, wherein

there are m blocks, where m is an integer greater than one,

each of said m blocks include k readout circuits, where k is an integer greater than one, and

a relationship between m and k is expressed by the equation k=m^1/2.

15. The device of claim 13, further comprising at least a first set of super-block select switches arranged in cascade fashion relative to said block select switches to further reduce the parasitic capacitance effects from non-driven signal readout lines.

16. A method of reducing parasitic capacitance effects in a device having a shared signal readout line, a plurality of signal readout lines including a selected signal readout line, said plurality of signal readout lines organized as a plurality of blocks each associated with at least two of said plurality of signal readout lines, and a plurality of block select switches each for selectively coupling the shared signal readout line to every signal readout line in a selected block from said plurality of blocks, the method comprising:

selecting one of said plurality of blocks as a selected block, wherein said selected block includes said selected signal line; and

enabling a block select switch corresponding to the selected block to couple every signal readout line in said selected block to said shared signal readout line; and

disabling the block switch corresponding to the selected block after a signal from the selected signal readout line is read out onto the shared signal readout line.

17. The method of claim 16, wherein the disabling of the enabled block switch occurs after all signal readout lines in the selected block having a signal to be read out onto the shared readout line are read out.

18. The method of claim 17, wherein the device further comprises at least a first set of super-block select switches arranged in cascade fashion relative to the block select switches to further reduce the parasitic capacitance effects from non-driven signal readout lines, the method further comprising:

selectively enabling a super-block select switch associated with the selected signal readout line during read out of the signal onto the shared readout line.

19. The method of claim 17, wherein the device is an active pixel sensor and the signal readout lines are associated signal lines from column readout circuits.

20. The method of claim 19, wherein the associated signal lines are a pair of differentiated pixel value signals, Vout_S, Vout R.

21. The method of claim 20, wherein the block select switches are transistors.

22. The method of claim 17, wherein

there are m blocks, where m is an integer greater than one

each of said m blocks include k readout lines, where k is an integer greater than one, and

a relationship between m and k is expressed by the equation k=m^1/2.