Network processor having cyclic redundancy check implemented in hardware
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1. A method for performing a Cyclic Redundancy Check (CRC) operation to generate a CRC result based on input data, the method comprising:
 receiving an instruction indicating the CRC operation is to be executed, the instruction including an indication of a polynomial to use in calculating the CRC result;
selecting one of a plurality of CRC circuits to obtain a selected CRC circuit to perform the CRC operation based on the indication of the polynomial in the instruction, each of the plurality of CRC circuits including a CRC polynomial hardwired therein;
receiving current CRC state data at the selected CRC circuit;
receiving the input data at the selected CRC circuit; and
generating the CRC result with the selected CRC circuit.
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Abstract
A network processor performs Cyclic Redundancy Check (CRC) operations using specialized hardware circuit. The network processor includes a plurality of hardwired CRC polynomials that are used to implement the CRC operations. A CRC instruction selects which polynomial to use when performing the CRC operation.
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22 Claims

1. A method for performing a Cyclic Redundancy Check (CRC) operation to generate a CRC result based on input data, the method comprising:

receiving an instruction indicating the CRC operation is to be executed, the instruction including an indication of a polynomial to use in calculating the CRC result;
selecting one of a plurality of CRC circuits to obtain a selected CRC circuit to perform the CRC operation based on the indication of the polynomial in the instruction, each of the plurality of CRC circuits including a CRC polynomial hardwired therein;
receiving current CRC state data at the selected CRC circuit;
receiving the input data at the selected CRC circuit; and
generating the CRC result with the selected CRC circuit.  View Dependent Claims (2, 3, 4, 5)


6. A network device comprising:

an instruction store including at least one Cyclic Redundancy Check (CRC) instruction relating to a CRC operation; and
an arithmetic logic unit (ALU) connected to the instruction store, the ALU including at least one CRC circuit for generating a CRC result based on hardwired CRC polynomials, the ALU receiving input data for the CRC operation and the CRC instruction, and in response to the CRC instruction, generating the CRC result using the CRC circuit, the input data, and a selected one of the hardwired polynomials, the selected hardwired polynomial being selected based on the CRC instruction.  View Dependent Claims (7, 8, 9, 10, 11)


12. A device comprising:

a first Cyclic Redundancy Check (CRC) circuit configured to perform a first CRC operation on input data, the first CRC operation being performed using a first polynomial, the first polynomial being hardwired into the first CRC circuit;
a second CRC circuit configured to perform a second CRC operation on the input data, the second CRC operation being performed using a second polynomial, the second polynomial being hardwired into the second CRC circuit; and
a demultiplexer for receiving an instruction indicating that a CRC operation is to be performed and indicating which of the first and second circuits is to perform the CRC operation thereby providing an indicated circuit, the demultiplexer enabling the indicated circuit to generate a CRC output result based on the input data.  View Dependent Claims (13, 14, 15, 16, 17, 18)


19. A network processor comprising:

means for issuing an instruction indicating that a Cyclic Redundancy Check (CRC) operation is to be initiated;
at least one CRC circuit for performing CRC operations using one of a plurality of CRC polynomials hardwired into the network processor; and
means for selecting the one of a plurality of CRC polynomials to use to perform the CRC operation based on contents of the instruction.  View Dependent Claims (20, 21, 22)

Specification