Pixel cell with high storage capacitance for a CMOS imager

• US 6,853,045 B2
• Filed: 04/11/2003
• Issued: 02/08/2005
• Est. Priority Date: 02/25/2000
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): FORDE, REMMON R
• Application Number:
  US10/411,158
• Publication Number:
  US 20030205773A1
• Time in Patent Office: 669 Days
• Field of Search: 257/462, 257/233, 257/231, 257/229, 257/225, 257/222, 257/461
• US Class Current: 257/462
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 μm² to about 10 μm². The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Claims

1. An optical sensing circuit comprising:

a first capacitive structure, the first capacitive structure being adapted to receive a plurality of photons and responsively produce a respective plurality of electric charges;

a second capacitive structure, the second capacitive structure being adapted to control an electrical current, the second capacitive structure comprising a conductive layer having an area of from about 0.3 μ

m² to about 25 μ

m²; and

an electrically conductive path, the electrically conductive path being coupled between the first capacitive structure and the second capacitive structure.

2. An optical sensing circuit as defined in claim 1 wherein the conductive layer has an area of from about 1.0 μ

m² to about 15 μ

m².

3. An optical sensing circuit as defined in claim 1 wherein the first capacitive structure comprises a photodiode.

4. An optical sensing circuit as defined in claim 3 wherein the photodiode comprises a PIN photodiode.

5. An optical sensing circuit as defined in claim 3 wherein the photodiode comprises a Schottky diode.

6. An optical sensing circuit as defined in claim 1 wherein the first capacitive structure comprises a photo gate.

7. An optical sensing circuit as defined in claim 1 wherein the second capacitive structure comprises a transistor gate stack.

8. An optical sensing circuit as defined in claim 1 wherein the electrically conductive path comprises a region of doped semiconductor material, the region of doped semiconductor material disposed in spaced relation to a transfer gate.

9. An optical sensing circuit as defined in claim 1 wherein the electrical current comprises a current received through a source follower transistor.