Data transfer controller and electronic device
First Claim
1. A data transfer control device for transferring data among a plurality of nodes that are connected to a bus, said data transfer control device comprising:
- a management circuit which manages an interface with a random accessible storage memory so that control information of a packet is written by a first upper layer into a control information area of said random accessible storage memory and data of said packet corresponding to said control information is written by a second upper layer into a data area different from said control information area of said random accessible storage memory said randomly accessible storage memory being divided into said control information area and said data area;
a packet assembly circuit which reads control information of said packet from said control information area and reads data of said packet corresponding to said control information from said data area; and
a link circuit which provides a service for transferring said read-out packet to each of nodes.
2 Assignments
0 Petitions
Accused Products
Abstract
The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. During IEEE 1394 data transfer, a packet assembly circuit (280) reads a header and data for a packet from header and data areas in a RAM (80) and links them together. The period of time during which a header CRC is created is used to obtain a data pointer. Whether a header or data is being read is determined by tcode, and the header pointer or data pointer incremented accordingly. A header is created while data is being fetched from the data area. Data is fetched to one channel which a packet is being transmitted from another channel within a divided send packet area. A linkage pointer is used to sequentially read a packet from another channel. An ACK code from the transfer destination is written back to the channel that sent the corresponding packet. Packets can be sent in series by rewriting a basic header to sequentially create headers until a number-of-repeats reaches zero.
16 Citations
15 Claims
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1. A data transfer control device for transferring data among a plurality of nodes that are connected to a bus, said data transfer control device comprising:
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a management circuit which manages an interface with a random accessible storage memory so that control information of a packet is written by a first upper layer into a control information area of said random accessible storage memory and data of said packet corresponding to said control information is written by a second upper layer into a data area different from said control information area of said random accessible storage memory said randomly accessible storage memory being divided into said control information area and said data area;
a packet assembly circuit which reads control information of said packet from said control information area and reads data of said packet corresponding to said control information from said data area; and
a link circuit which provides a service for transferring said read-out packet to each of nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification