Method and apparatus for processing events in a multithreaded processor

• US 6,857,064 B2
• Filed: 11/30/2001
• Issued: 02/15/2005
• Est. Priority Date: 12/09/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rodgers, S. Dion, Smith, Lawrence O.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US10/006,348
• Publication Number:
  US 20020116600A1
• Time in Patent Office: 1,173 Days
• Field of Search: 712/228, 712/244, 710/260
• US Class Current: 712/244
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

In a multithreaded processor, events are categorized according to which of a “soft” state clearing (“nuke”) process and a “hard” nuke process should be performed in response to each event. When an event is detected for a thread, either the soft nuke or hard nuke process is executed, according to the type of event, prior to invoking an event handler. The soft nuke process performs less than all of the actions performed by the hard nuke process and requires much less time to execute. If multiple threads are being processed, the hard nuke process requires synchronization between the threads and clears state for each thread, whereas the soft nuke process does not require cross-thread synchronization and clears state only for the thread in which the event was detected. In one embodiment, the soft nuke process is implemented in microcode, while the hard nuke process is hardware-implemented.

Claims

1. A processor comprising:

retirement logic from which microinstructions for both a first thread and a second thread being processed within the processor are retired; and

an event detector, coupled to the retirement logic, to detect an event for the first thread;

responsive to the detection of the event, to determine whether to execute a first state clearing process or a second state clearing process; and

to execute either the first state clearing process or the second state clearing process, depending on the event.

2. A processor as recited in claim 1, wherein the second state clearing process requires synchronization between the first and second threads, and wherein the first state clearing process does not require synchronization between the first and second threads.

3. A processor as recited in claim 1, wherein the first state clearing process clears state for only one of the first thread and the second thread, and the second state clearing process clears state for both the first thread and the second thread.

4. A processor as recited in claim 1, wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.

5. A processor as recited in claim 4, wherein the first state clearing process requires substantially less time to execute than the second state clearing process.

6. A processor as recited in claim 1, wherein the first state clearing process comprises clearing state for the first thread and not clearing state for the second thread.

7. A processor as recited in claim 6, wherein the second state clearing process comprises:

monitoring the second thread to detect a clearing point for the second thread; and

in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.

8. A processor as recited in claim 1, wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.

9. A processor as recited in claim 8, wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.

10. A processor as recited in claim 8, wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.

11. A processor as recited in claim 8, wherein the predetermined set of memory ordering conflict events comprises a memory alias event.

12. A processor as recited in claim 1, wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.

13. A processor as recited in claim 12, wherein the multithreaded processor comprises a store buffer to buffer store operations, wherein the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.

14. A processor as recited in claim 1, wherein the first state clearing process is software-implemented and the second state clearing process is hardware implemented.

15. A processor as recited in claim 1, wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.

16. A microprocessor comprising:

means for detecting an event for a first thread being processed in the microprocessor, the microprocessor also having a second thread being processed concurrently with the first thread;

means for determining, in response to detecting the event, whether a first state clearing process is to be used responsive to the event; and

means for executing the first state clearing process if the first state clearing process is to be used responsive to the event, the first state clearing process clearing state for only the first thread, and for executing the second state clearing process if the second state clearing process is to be used responsive to the event, the second state clearing process clearing state for both the first thread and the second thread.

17. A microprocessor as recited in claim 16, wherein the second state clearing process requires synchronization between the first and second threads, and wherein the first state clearing process does not require synchronization between the first and second threads.

18. A microprocessor as recited in claim 16, wherein the first state clearing process comprises clearing state for the first thread independently of the second thread.

19. A microprocessor as recited in claim 18, wherein the second state clearing process comprises:

monitoring the second thread to detect a clearing point for the second thread; and

in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.

20. A microprocessor as recited in claim 16, further comprising categorizing a plurality of events which may occur in the multithreaded processor according to which of the first state clearing process and the second state clearing process is to be performed in response to each event.

21. A microprocessor as recited in claim 16, wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.

22. A microprocessor as recited in claim 16, wherein the first state clearing process requires substantially less time to execute than the second state clearing process.

23. A microprocessor as recited in claim 16, wherein the first state clearing process is software-implemented and the second state clearing process is hardware-implemented.

24. A microprocessor as recited in claim 16, wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.

25. A microprocessor as recited in claim 24, wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.

26. A microprocessor as recited in claim 24, wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.

27. A microprocessor as recited in claim 24, wherein the predetermined set of memory ordering conflict events comprises a memory alias event.

28. A microprocessor as recited in claim 16, wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.

29. A microprocessor as recited in claim 28, wherein the multithreaded processor comprises a store buffer to buffer store operations, wherein the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.

30. A microprocessor as recited in claim 16, wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.

31. A machine-readable storage medium storing instructions which, when executed by a multithreaded processor, cause the processor to perform a method comprising:

detecting an event for a first thread being processed in the multithreaded processor, the multithreaded processor also having a second thread being processed concurrently with the first thread;

in response to detecting the event, determining whether a first state clearing process is to be used responsive to the event;

if the first state clearing process is to be used responsive to the event, then executing the first state clearing process, the first state clearing process clearing state for only the first thread; and

if the first state clearing process is not to be used responsive to the event occurrence, then executing a second state clearing process responsive to the event, the second state clearing process clearing state for both the first thread and the second thread.

32. A machine-readable storage medium as recited in claim 31, wherein the second state clearing process requires synchronization between the first and second threads, and wherein the first state clearing process does not require synchronization between the first and second threads.

33. A machine-readable storage medium as recited in claim 32, wherein the first state clearing process comprises clearing state for the first thread independently of the second thread.

34. A machine-readable storage medium as recited in claim 31, wherein the second state clearing process comprises:

monitoring the second thread to detect a clearing point for the second thread; and

in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.

35. A machine-readable storage medium as recited in claim 31, further comprising categorizing a plurality of events which may occur in the multithreaded processor according to which of the first state clearing process and the second state clearing process is to be performed in response to each event.

36. A machine-readable storage medium as recited in claim 31, wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.

37. A machine-readable storage medium as recited in claim 31, wherein the first state clearing process requires substantially less time to execute than the second state clearing process.

38. A machine-readable storage medium as recited in claim 31, wherein the first state clearing process is software-implemented and the second state clearing process is hardware-implemented.

39. A machine-readable storage medium as recited in claim 31, wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.

40. A machine-readable storage medium as recited in claim 39, wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.

41. A machine-readable storage medium as recited in claim 39, wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.

42. A machine-readable storage medium as recited in claim 39, wherein the predetermined set of memory ordering conflict events comprises a memory alias event.

43. A machine-readable storage medium as recited in claim 31, wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.

44. A machine-readable storage medium as recited in claim 43, wherein the multithreaded processor comprises a store buffer to buffer store operations, where in the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.

45. A machine-readable storage medium as recited in claim 31, wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.

46. A method comprising:

categorizing a plurality of events that can occur in a multithreaded processor according to which of a plurality of state clearing processes is to be performed in response to each event, the plurality of state clearing processes including a first state clearing process and a second state clearing process, the first state clearing process to clear state for only one of a plurality of threads being processing concurrently in the processor, the second state clearing process to clear state for at least two of said plurality of threads;

in response to detecting an event in the processor, determining whether to execute the first state clearing process or the second state clearing process, according to a type of the event; and

executing either the first state clearing process or the second state clearing process, according to the outcome of said determining.

47. A method as recited in claim 46, wherein the first state clearing process includes a first plurality of actions and the second state clearing process includes a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions.

48. A method as recited in claim 47, wherein the first state clearing process requires substantially less time to execute than the second state clearing process.

49. A method as recited in claim 46, wherein the first state clearing process comprises clearing state for the first thread independently of the second thread.

50. A method as recited in claim 49, wherein the second state clearing process comprises:

monitoring the second thread to detect a clearing point for the second thread; and

in response to detection of the clearing point for the second thread, clearing state for both the first thread and the second thread.

51. A method as recited in claim 46, wherein the first state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.

52. A method as recited in claim 51, wherein the predetermined set of memory ordering conflict events comprises a multithreaded snoop.

53. A method as recited in claim 51, wherein the predetermined set of memory ordering conflict events comprises an external processor snoop.

54. A method as recited in claim 51, wherein the predetermined set of memory ordering conflict events comprises a memory alias event.

55. A method as recited in claim 46, wherein the second state clearing process is identical for each event in response to which it is used, and wherein the first state clearing process varies according to the event in response to which it is used.

56. A method as recited in claim 46, wherein the multithreaded processor comprises a store buffer to buffer store operations, wherein the second state clearing process comprises clearing the store buffer, and wherein the first state clearing process comprises clearing the store buffer only in response to certain events and not in response to other events.

57. A method as recited in claim 46, wherein the first state clearing process is software-implemented and the second state clearing process is hardware implemented.

58. A method as recited in claim 46, wherein the first state clearing process and the second state clearing process each comprise clearing the state of an instruction pipeline of the multithreaded processor.

61. A method as recited in claim 46, wherein the software-implemented state clearing process is executed if the event is one of a predetermined set of memory ordering conflict events.

59. A method comprising:

categorizing a plurality of events which may occur in a multithreaded processor according to which of a plurality of state clearing processes can be performed in response to each event, each of the plurality of state clearing processes capable of execution in the multithreaded processor, the plurality of state clearing processes including a software-implemented state clearing process and a hardware-implemented state clearing process, the software-implemented state clearing process including a first plurality of actions and the hardware implemented state clearing process including a second plurality of actions, the first plurality of actions being a partial subset of the second plurality of actions, wherein the software-implemented state clearing process requires substantially less time to execute than the hardware-implemented state clearing process;

detecting an event for a first thread being processed in the multithreaded processor, the multithreaded processor also having a second thread being processed concurrently with the first thread;

in response to detecting the event, determining whether the software implemented state clearing process can be used responsive to the event;

if the software-implemented state clearing process can be used responsive to the event, then executing the software-implemented state clearing process, including clearing state in the multithreaded processor for the first thread but not the second thread, wherein said clearing state for the first thread is done independently of the second thread;

if the software-implemented state clearing process cannot be used responsive to the event occurrence, then executing the hardware-implemented state clearing process responsive to the event, the hardware-implemented state clearing process including

monitoring the second thread to detect a clearing point for the second thread, and

in response to detection of the clearing point for the second thread, clearing state within the multithreaded processor for both the first thread and the second thread;

and

invoking an event handler to service the event after executing the software-implemented state clearing process or the hardware-implemented state clearing process.

60. A method as recited in claim 59, wherein the hardware-implemented state clearing process requires synchronization between the first and second threads, and wherein the software-implemented state clearing process does not require synchronization between the first and second threads.