Method and apparatus to facilitate self-testing of a system on a chip

  • US 6,857,092 B1
  • Filed: 05/25/2001
  • Issued: 02/15/2005
  • Est. Priority Date: 08/17/2000
  • Status: Active Grant
First Claim
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1. A system-on-a-chip comprising:

  • a processor;

    a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor; and

    a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly; and

    a test isolation signal to isolate a portion of the CSL during testing.

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