Partially processed tunnel junction control element

• US 6,858,883 B2
• Filed: 06/03/2003
• Issued: 02/22/2005
• Est. Priority Date: 06/03/2003
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter J., Nickel, Janice H.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/454,552
• Publication Number:
  US 20040245544A1
• Time in Patent Office: 630 Days
• Field of Search: 257/104, 257/530, 257/5, 257/52, 257/295, 257/296, 365/163, 365/51
• US Class Current: 257/104
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Abstract

A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.

Claims

1. A system, comprising:

a memory storage element;

a tunnel junction control element that is partially-processed such that a density of oxidation or nitriding is substantially higher in one portion of the control element than in another portion of the control element and

a first electrode located between the memory storage element and the tunnel junction control element.

2. The system of claim 1, wherein a breakdown voltage of the tunnel Junction control element is greater than three volts (in either direction forward or reversed).

3. The system of claim 1, wherein the breakdown voltage of the partially processed tunnel junction control element is greater than the break-down voltage of the tunnel junction memory storage element.

4. The system of claim 1, wherein the tunnel junction control element is formed from an oxide.

5. The system of claim 1, wherein the tunnel junction control element extends substantially horizontally, and the memory storage element extends substantially horizontally, wherein the tunnel Junction control element and the memory storage element are vertically separated.

6. The system of claim 1, wherein the tunnel junction control element extends substantially horizontally, and the memory storage element extends substantially horizontally, and wherein the tunnel junction control element is horizontally spaced from the memory storage element.

7. The system of claim 1, wherein the tunnel junction control element is vertically spaced from the memory storage element.

8. The system of claim 1, wherein the tunnel junction control element is partially-processed by being oxidized.

9. The system of claim 1, wherein the partial processing of the tunnel junction control element is provided using a plurality of portions, at least one of the plurality of portions is not oxidized or nitrided while at least one of the plurality of portions is oxidized or nitrided.

10. The system of claim 1, wherein the memory storage element, the electrode, and the tunnel junction control element are all included in an integrated circuit.

11. The system of claim 1, wherein the system is a memory system.

12. The system of claim 1, further comprising a second electrode and a third electrode, wherein the memory storage element and the tunnel junction control element are both located between the second electrode and the third electrode.

13. The system of claim 12, wherein the memory storage element includes an oxide of the second electrode.

14. The system of claim 12, wherein the tunnel junction control element includes an oxide of the third electrode.

15. The system of claim 12, wherein the memory storage element includes a nitride of the second electrode.

16. The system of claim 12, wherein the tunnel junction control element includes a nitride of the third electrode.

17. The system of claim 1, further comprising a plurality of memory cells, each one of the plurality of memory cells includes a conductive tub, wherein multiple ones of the memory cells are implemented in stacked layers, wherein a conductor is vertically adjacent arm edge of an adjacent conductive tub.

18. The system of claim 1, wherein a cross-sectional area of the control element differs from the cross-sectional area of the memory storage element.

19. The system of claim 1, wherein the difference in cross-sectional area of the control element and the memory storage element provides an increased break down voltage of the control element compared to the break down voltage of the memory storage element.

20. The system of claim 1, wherein the memory storage element includes a fuse device.

21. The system of claim 1, wherein the memory storage device includes an antifuse device.

22. The system of claim 1, wherein the memory storage device includes a switch.

23. The system of claim 1, wherein the memory storage device includes a charge storage device.

24. The system of claim 1, wherein the materials used to form the memory storage device is selected from a group of materials, the group of materials include a resisitive material, a trap-induced hysteresis material, a ferroelectric capacitor material, a polymetric capacitor material, a Hall Affect material, and a tunneling magneto-resistive material.

25. The system of claim 1, wherein the memory storage element comprises an antifuse including material selected from a group of materials, the group of materials including an oxidized metal tunnel junction, a silicon dioxide tunnel junction, a dielectric-rupture, a polysilicon semiconductor, a polycrystalline semiconductor, an amophous semiconductor, a microcrystalline semiconductor, a metal filament electro-migration semiconductor, and a polysilicon resistor semiconductor.

26. The system of claim 1, wherein the memory storage element includes a rewritable phase change material.

27. The system of claim 1, wherein the memory storage element includes an organic phase change material.

28. A memory structure comprising:

a plurality of layers of memory cells;

each memory cell of the plurality of layers of memory cells including a first electrode, a second electrode, a third electrode, a memory storage element disposed between the second electrode and the third electrode, and a control element disposed between the first electrode and the second electrode; and

the memory storage element having a density of oxidation or nitriding substantially higher than a density of oxidation or nitriding of the control element such that a breakdown voltage of the store element is lower than a breakdown voltage of the control element.

29. The memory structure of claim 28, wherein the control element is partially oxidized or nitrided.

30. The memory structure of claim 29, wherein the partial oxidation or nitriding results from oxidizing or nitriding the control element for a shorter duration than for a fully oxidized or nitrided control element.

31. The memory structure of claim 29, wherein the partial oxidation or nitriding results from the control element including a plurality of layers, certain of the layers of the control element are not oxidized or nitrided while certain ones of the layers of the control element are completely oxidized or nitrided.

32. The memory structure of claim 28, wherein the memory storage element is vertically spaced from the control element.

33. The memory structure of claim 28, wherein the memory storage element is horizontally spaced from the control element.

34. The system of claim 28, further comprising a plurality of memory cells, each one of the plurality of memory cells includes a conductive tub, wherein a plurality of the memory cells are implemented in stacked layers, wherein a conductor that is vertically adjacent the rim edge of a given conductive tub is vertically adjacent the base of a conductive tub that is in an adjacent layer.