Memory device with sense amplifier and self-timed latch

  • US 6,862,208 B2
  • Filed: 04/11/2003
  • Issued: 03/01/2005
  • Est. Priority Date: 04/11/2003
  • Status: Active Grant
First Claim
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1. A memory device, comprising:

  • a plurality of memory cells, each of the plurality of memory cells coupled to a bit line;

    a sense amplifier for amplifying a data signal from a selected one of the plurality of memory cells via the bit line to provide an amplified data signal in response to asserting a sense enable signal;

    an isolation circuit, coupled between the bit line and the sense amplifier, the isolation circuit for decoupling the selected one of the plurality of memory cells from the sense amplifier at about the same time as the assertion of the sense enable signal; and

    a self-timed storage device, coupled to the sense amplifier, for storing data corresponding to the amplified data signal only in response to the amplified data signal.

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