Fabrication of a bipolar transistor using a sacrificial emitter

• US 6,869,853 B1
• Filed: 12/18/2002
• Issued: 03/22/2005
• Est. Priority Date: 12/18/2002
• Status: Expired due to Term

• Current Assignee: Viewpoint IP LLC (IP Edge LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Gopalan, Prabhuram
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US10/323,002
• Time in Patent Office: 825 Days
• Field of Search: 438/321, 257/198
• US Class Current: 438/321
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/66287 with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation H01L29/6628 takes precedence
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Abstract

In one embodiment, a transistor is fabricated by forming a sacrificial emitter over a base, forming an oxide layer over the sacrificial emitter, removing a portion of the oxide layer, and then removing the sacrificial emitter. An emitter is later formed in the space formerly occupied by the sacrificial emitter. The sacrificial emitter allows a base implant step to be performed early in the process using a single masking step. The base may comprise epitaxial silicon-germanium or silicon.

Claims

1. A method of fabricating a bipolar transistor, the method comprising:

forming a sacrificial emitter over a base;

forming a first oxide layer over the sacrificial emitter;

forming a masking material over the first oxide layer;

planarizing the masking material to expose the first oxide layer;

etching a portion of the first oxide layer over the sacrificial emitter; and

removing the sacrificial emitter.

2. The method of claim 1 wherein the base comprises silicon-germanium (SiGe).

3. The method of claim 1 wherein the sacrificial emitter comprises:

a polysilicon material over a second oxide layer.

4. The method of claim 1 further comprising:

after forming the sacrificial emitter but prior to forming the first oxide layer, implanting a dopant in an extrinsic base region.

5. The method of claim 1 wherein the base comprises silicon.

6. The method of claim 1 wherein removing the sacrificial emitter comprises:

etching the sacrificial emitter using a second oxide layer as an etch stop; and

etching the second oxide layer to expose the base.

7. The method of claim 1 further comprising:

forming a polysilicon material on the base.

8. The method of claim 1 wherein forming the masking material over the first oxide layer comprises spin-coating a photoresist material.

9. The method of claim 1 wherein planarizing the masking material comprises performing an etch-back process.

12. The method of claim 1 wherein the masking material comprises photoresist.

10. A method of forming a bipolar transistor, the method comprising:

implanting a dopant in a silicon-germanium (SiGe) layer that is under a sacrificial emitter;

depositing a first oxide layer over the sacrificial emitter;

forming a mask over the first oxide layer;

isotropically etching the first oxide layer to create an undercut under the mask and fully expose a top portion of the sacrificial emitter; and

replacing the sacrificial emitter with an emitter.

11. The method of claim 10 wherein replacing the sacrifical emitter with an emitter comprises:

etching the sacrificial emitter to expose a second oxide layer;

etching the second oxide layer to expose the SiGe layer; and

forming the emitter in a volume previously occupied by the sacrificial emitter.

13. A method of fabricating a bipolar transistor, the method comprising:

forming a sacrificial emitter over a base;

forming a first oxide layer over the sacrificial emitter;

forming a masking material over the sacrificial emitter such that a portion of the first oxide layer is exposed;

isotropically etching the first oxide layer to create an undercut under the masking material and fully expose a top portion of the sacrificial emitter; and

removing the sacrificial emitter.

14. The method of claim 13 wherein isotropically etching the first oxide layer comprises wet etching the first oxide layer.

15. The method of claim 13 wherein the base comprises silicon-germanium (SiGe).

16. The method of claim 13 wherein the sacrificial emitter comprises:

a polysilicon material over a second oxide layer.

17. The method of claim 13 further comprising:

after forming the sacrificial emitter but prior to forming the first oxide layer, implanting a dopant in an extrinsic base region.