Chip scale package with heat dissipating part

• US 6,876,087 B2
• Filed: 02/12/2003
• Issued: 04/05/2005
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Ho, Kwun-Yao, Kung, Moriss
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/248,714
• Publication Number:
  US 20040036180A1
• Time in Patent Office: 783 Days
• Field of Search: 257/778, 257/712, 257/675, 257/666, 257/684, 257/696, 257/796, 257/692, 257/693, 257/784, 257/786, 257/787, 257/734, 257/737, 257/738, 257/783, 257/676, 257/673, 257/776, 257/753
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

In a chip scale package, a chip is mounted in a cavity formed in a leadframe. The leadframe includes a plurality of leads that radiate from a heat dissipating part located in the cavity. Each lead extends from a thinner portion of inner lead in the cavity to a thicker portion of outer lead outside the cavity. The chip includes a plurality of bonding pads on which is respectively formed a layer of connecting material. The chip is attached on the heat dissipating material, and via the layer of connecting material, is electrically connected to the inner leads by thermal pressing. Via molding, the chip is encapsulated in the leadframe. The achieved package has a dimensional size that is approximately equal to that of the leadframe with an improved thermal dissipation.

Claims

1. A structure of a chip scale package (CSP) on a printed circuit board, comprising:

a chip, having a chip thickness and a plurality of exposed bonding pads;

a leadframe, including a heat dissipating part and a plurality of leads that radiate from the heat dissipating part, each of the leads extending from an inner lead portion having a first thickness proximate to the heat dissipating part and an outer lead portion having a second thickness greater than the first thickness, wherein a difference of the first thickness and the second thickness is slightly greater than the chip thickness;

an adhesive layer, used to adhere the chip to the heat dissipating part;

a first connecting material layer, used to allow the bonding pads to electrically connect to the inner lead portion when the chip is adhered to the heat dissipating part;

an encapsulant, encapsulating the chip in the leadframe, wherein the dissipating part has an exposed surface opposite to the chip, wherein the exposed surface of the heat dissipating part and a surface of the loads have the same level, wherein a surface of the chip opposite to the heat dissipating part is exposed and is substantially at a same surface level with the outer lead portion; and

a circuit board; and

a second connecting material layer, located on the outer lead with the second thickness, used to allow the outer lead portion to be electrically contact with the circuit board, wherein the heat dissipating part remained exposed.

2. The structure of claim 1, wherein the first connecting material layer includes an electric connecting bump with direct contact between the chip and the inner lead portion.

3. The structure of claim 1, wherein the second connecting material layer includes solder paste.

4. The structure of claim 1, further comprising an additional heatsink layer between a rear surface of the chip and the circuit board, at a space defined by the second connecting material layer.

5. The structure of claim 1, wherein the second thickness of the outer lead is substantially uniform.