Memory device test system and method

• US 6,880,117 B2
• Filed: 06/14/2002
• Issued: 04/12/2005
• Est. Priority Date: 06/14/2002
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Tseng, Chin-Chung, Lin, Wen-Hsi
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US10/172,059
• Publication Number:
  US 20030233604A1
• Time in Patent Office: 1,033 Days
• Field of Search: 714/718, 714/736, 714/719, 714/738, 714/743, 714/744, 702/124, 702/117, 702/118, 324/527, 324/528
• US Class Current: 714/718
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device. In another embodiment, the first clock signal is not used and the address signals are synchronized to every two cycles of the second clock signal. A method for testing a memory device, which may be embodied in the testing system, is also described.

Claims

1. A testing system comprising:

a timing generator constructed to generate a clock signal that is to be provided as an input timing signal to a memory device under test;

a pattern generator configured to produce an address signal; and

a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to every x cycles of the clock signal wherein x is greater than 1;

wherein during a data read and compare generator, the pattern generator and the waveform shaping circuit are configured to;

(i) produce a control signal, a strobe signal, and expected data, wherein the control signal directs the memory device to provide stored data at an address specified by the address signal, and (ii) provide the control signal to the memory device along with the address signal;

wherein the wave form shaping circuit provides the address signal to the memory device for x cycles of the clock signal;

wherein the testing system produces the strobe signal during only one cycle of the x cycles of the clock signal;

wherein x is an integer; and

wherein the testing system is configured to first perform the read and compare operation for even addresses in an address space of the memory device, and to then perform the read and compare operation for odd addresses in the address space of the memory device.

2. A testing system comprising:

a timing generator constructed to generate a clock signal that is to be provided as an input timing signal to a memory device under test;

a pattern generator configured to produce an address signal; and

a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to every x cycles of the clock signal wherein x is greater than 1;

wherein x is equal to 2;

wherein the clock signal comprises rising edge transition or a falling transition;

wherein the clock signal is asserted or either a rising edge transition or a falling edge transition of the clock signal; and

wherein the address signal remains asserted for two cycles of the clock signal after being asserted.

3. The testing system as recited in claim 2, wherein during a data read and compare operation, the pattern generator and the waveform shaping circuit are configured to:

(i) produce a control signal, a strobe signal, and expected data, wherein the control signal directs the memory device to provide stored data at an address specified by the address signal, and (ii) provide the control signal to the memory device along with the address signal.

4. The testing system as recited in claim 3, wherein the pattern generator provides the address signal to the memory device for two cycles of the second clock signal, and wherein the testing system produces the strobe signal during only one cycle of the 2 cycles of the clock signal.

5. The testing system as recited in claim 4, further comprising:

a data comparator coupled to receive data from the memory device, the expected data, and the strobe signal, and configured to respond to the strobe signal by comparing the data received from the memory device and the expected data, and to produce failure data if the data received from the memory device is not equal to the expected data; and

a failure analysis memory coupled to receive the address signal produced by the pattern generator and the failure data produced by the data comparator, wherein the failure analysis memory is configured to respond to the failure data by storing an address conveyed by the address signal.

6. A testing system, comprising:

a timing generator constructed to generate a first clock signal;

a frequency multiplier circuit coupled to receive the first clock signal and configured to produce a second clock signal having a frequency greater than a frequency of the first clock signal, and to provide the second clock signal to a memory device;

a pattern generator coupled to receive the first clock signal and to produce an address signal; and

a waveform shaping circuit operatively coupled to the pattern generator, the waveform shaping circuit being constructed to receive the address signal from the pattern generator and to provide the address signal to the memory device synchronized to the first clock signal.

7. The testing system as recited in claim 6, wherein the frequency of the second clock signal is an integer multiple of the frequency of the first clock signal.

8. The testing system as recited in claim 6, wherein operations within the memory device are synchronized to the second clock signal.

9. The testing system as recited in claim 6, wherein the waveform shaping circuit provides the address signal to the memory device for one cycle of the first clock signal, and for more than one cycle of the second clock signal.

10. The testing system as recited in claim 6, wherein the first clock signal comprises rising edge transitions and falling edge transitions, and wherein the address signal is asserted on either a rising edge transition or a falling edge transition of the first clock signal, and wherein the address signal remains asserted for at least one cycle of the first clock signal after being asserted.

11. The testing system as recited in claim 6, wherein during a data write operation, the pattern generator and the waveform shaping circuit are configured to:

(i) produce a control signal and a data signal synchronized to the first clock signal, wherein the control signal directs the memory device to store the data at an address specified by the address signal, and (ii) provide the control and data signals to the memory device along with the address signal.

12. The testing system as recited in claim 13, further comprising:

a data comparator coupled to receive data from the memory device, and the expected data and the strobe signal, and configured to respond to the strobe signal by comparing the data received from the memory device and the expected data, and to produce failure data if the data received from the memory device is not equal to the expected data; and

a failure analysis memory coupled to receive the address signal produced by the pattern generator and the failure data produced by the data comparator, wherein the failure analysis memory is configured to respond to the failure data by storing an address conveyed by the address signal.

13. The testing system as recited in claim 6, wherein during a data read and compare operation, the pattern generator and the waveform shaping circuit are configured to:

(i) produce a control signal, a strobe signal, and expected data, wherein the control signal directs the memory device to provide stored data at an address specified by the address signal, and (ii) provide the control signal to the memory device along with the address signal.

14. The testing system as recited in claim 13, wherein the waveform shaping circuit provides the address signal to the memory device for more than one cycle of the second clock signal, and wherein the testing system produces the strobe signal during a first cycle of the more than one cycle of the second clock signal.

15. The testing system as recited in claim 14, wherein the tester is configured to first perform the data read and compare operation for even addresses in an address space of the memory device, and to then perform the data read and compare operation for odd addresses in the address space of the memory device.

16. A method for testing a memory device, comprising:

providing a clock signal to a memory device such that operation within the memory device are synchronized to the clock signal;

reading the data from the memory device using an address signal synchronized to every x cycles of the clock signal wherein x is greater than 1; and

comparing the data read from the memory device to test data;

wherein the providing comprises generating a clock signal having rising edge transitions and falling edge transitions; and

wherein the reading is preceded with writing test data to the memory device using the address signal, the address signal being asserted on either a rising edge transition or a falling edge transition of the first clock signal, and remaining asserted for at least one x cycles of the first clock signal alter being asserted.

17. The method as recited in claim 16, wherein the writing comprises providing the address signal, and test data corresponding to the address signal, to the memory device during an operation to store the test data within the memory device at an address corresponding to the address signal, wherein the address signal is synchronized to every x cycles of the clock signal.

18. A method for testing a memory device comprising:

providing a clock signal to a memory device such that operation within the memory device are synchronized to the clock signal;

reading the data from the memory device using an address signal synchronized to every x cycles of the clock signal wherein x is greater than 1; and

comparing the data read from the memory device to test data;

wherein the reading comprises providing the address signal to the memory device during the operation to retrieve data stored within the memory device at an address corresponding to the address signal, the address signal being provided to the memory device for x cycles of the clock signal; and

wherein the comparing comprises producing a strobe signal during only one cycle of the x cycles of the clock signal, to thereby acquire data from the memory device.

19. The method as recited in claim 18, wherein the address signal is provided to the memory device for 2 cycles of the clock signal, and wherein the strobe signal is produced for only one cycle of the 2 cycles of the clock signal.

20. A method for testing a memory device, comprising:

using a first clock signal to produce a second clock signal having a frequency greater than a frequency of the first clock signal;

providing the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal;

reading data from the memory device using an address signal synchronized to the first clock signal; and

comparing the data retrieved from the memory device during the reading to the test data.

21. The method as recited in claim 20, wherein the using comprises using the first clock signal to produce a second clock signal having a frequency that is an integer multiple of the first clock signal.

22. The method as recited in claim 20, wherein:

the using comprises generating a first clock signal having rising edge transitions and falling edge transitions; and

the reading is preceded with writing test data to the memory device using the address signal, the address signal being asserted on either a rising edge transition or a falling edge transition of the first clock signal, and remaining asserted for at least one cycle of the first clock signal after being asserted.

23. The method as recited in claim 22, wherein the writing comprises providing an address signal, and test data corresponding to the address signal, to the memory device during an operation to store the test data within the memory device at an address corresponding to the address signal, wherein the address signal is synchronized to the first clock signal.

24. The method as recited in claim 20, wherein:

the reading comprises providing the address signal to the memory device during an operation to retrieve data stored within the memory device at an address corresponding to the address signal, the address signal being provided to the memory device for more than one cycle of the second clock signal; and

the comparing comprises producing a strobe signal during only a first cycle of the more than one cycle of the second clock signal, to thereby acquire data from the memory device.

25. A method for testing a memory device, comprising:

providing a clock into the memory device;

inputting an address into the memory device, each address being synchronized with every two cycles of the clock;

outputting an output data from the memory device according to the address, the output data being synchronized with every cycle of the clock;

retrieving odd or even, but not both, of the output data; and

comparing the retrieved output data with corresponding even of a standard data.

26. The method of claim 25, wherein the inputting comprises inputting an even address, the outputting comprises outputting a first data output from the memory device, the retrieving comprises retrieving odd of the first output data, and the comparing further comprises comparing the odd of the first output data with even of a standard data;

and wherein the method further comprises;

inputting an odd address into the memory device, each odd address being synchronized with every two cycles of the clock;

outputting a second output data from the memory device according to the odd address, the second output data being synchronized with every cycle of the clock;

retrieving odd of the second output data; and

comparing the odd of the second output data with corresponding odd of the standard data.

27. The method of claim 26, further comprising generating a record of comparisons of the odd of the first output data with even of the standard data and the odd of the second output data with odd of the standard data.

28. A method for testing a memory device, comprising:

generating a first clock signal;

using the first clock signal to produce a second clock signal having a frequency greater than a frequency of the first clock signal;

providing the second clock signal to a memory device such that operations within the memory device are synchronized to the second clock signal;

performing a read and compare operation for each of the even addresses in the address space of the memory device, wherein each read and compare operation comprises (i) providing an address signal to the memory device to retrieve data stored within the memory device at the address wherein the address signal is synchronized to the first clock signal, and (ii) comparing the retrieved data to the test data;

performing a read and compare operation for each of the odd addresses in the address space of the memory device, wherein each read and compare operation comprises (i) providing an address signal to the memory device to retrieve data stored within the memory device at the address, wherein the address signal is synchronized to the first clock signal, and (ii) comparing the retrieved data to the test data.

29. The method as recited in claim 28, wherein:

the performing of a read and compare operation for each of the even addresses is preceded by a step of performing a write operation for each even address in an address space of the memory device, wherein each even-address write operation comprises providing an even address signal and test data corresponding to the even address signal to the memory device to store the test data within the memory device at an address corresponding to the even address signal, and wherein the even address signal is synchronized to the first clock signal; and

the performing of a read and compare operation for each of the odd addresses is preceded by a step of performing a write operation for each odd address in an address space of the memory device, wherein each odd-address write operation comprises providing an odd address signal and test data corresponding to the odd address signal to the memory device to store the test data within the memory device at an address corresponding to the odd address signal, and wherein the odd address signal is synchronized to the first clock signal.