Method of manufacturing a semiconductor device to provide a plurality of test element groups (TEGs) in a scribe region

• US 6,881,597 B2
• Filed: 01/22/2002
• Issued: 04/19/2005
• Est. Priority Date: 01/22/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Arakawa, Fumiko, Asayama, Kyoichiro, Mitsui, Yasuhiro, Kamohara, Shiro, Ohji, Yuzuru
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US10/051,056
• Publication Number:
  US 20030006795A1
• Time in Patent Office: 1,183 Days
• Field of Search: 438/17, 438/18, 324/765, 257/48
• US Class Current: 438/18
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 μm or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 μm to 0.8 μm to the first electrode pad.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming a bonding pad and an extraction electrode each comprised of an uppermost layer wiring in a product circuit region;

(b) forming a protection film on an upper layer of said uppermost layer wiring; and

(c) partially exposing a surface of said bonding pad by removing a predetermined part of said protection film,

wherein said uppermost layer wiring is formed by depositing a conductive body and then patterning by a lithography method,

a plurality of logic circuits provided with said extraction electrode are formed in said product circuit region, and

after partially exposing the surface of said extraction electrode by removing said protection film on said extraction electrode, a probe having a tip radius of curvature of about 0.05 μ

m to 0.8 μ

m is contacted to said extraction electrode, and then logic values of said logic circuits are evaluated.

2. The method of manufacturing a semiconductor device according to claim 1;

wherein said protection film on said extraction electrode is removed by a focused ion beam method or a selective etching method.

3. The method of manufacturing a semiconductor device according to claim 1;

wherein said logic circuit comprises n input terminals and m output terminals, and n+m+3 probes are contacted to said extraction electrodes to evaluate a logic value of said logic circuit.

4. The method of manufacturing a semiconductor device according to claim 3,

wherein one of said probes is a probe for contact confirmation.

5. The method of manufacturing a semiconductor device according to claim 1,

wherein said probe contains tungsten as a main component.

6. The method of manufacturing a semiconductor device according to claim 1,

wherein said logic circuits are TEG elements.