Highly stable integrated time reference

• US 6,882,235 B2
• Filed: 10/28/2003
• Issued: 04/19/2005
• Est. Priority Date: 01/18/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gloerstad, Terje, Kappes, Mike
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US10/695,180
• Publication Number:
  US 20040085146A1
• Time in Patent Office: 539 Days
• Field of Search: 331/137, 331/135, 331/111, 331/36.C
• US Class Current: 331/135
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Claims

1. A system for calibrating an RC time constant of an integrated clock, comprising:

a register for storing a reset number;

a counter coupled to receive the reset number from the register and further coupled to receive clock cycles from an RC oscillator;

a master counter for receiving a reset signal from the counter, which reset signal is generated by the counter whenever the number of clock cycles that is received from the RC oscillator matches the reset number received from the register;

the master counter being further coupled to receive clock signals from a master clock, which master counter generates a count value, which count value reflects the number of clock cycles received from the master clock since the last reset signal was received; and

calibration circuitry coupled to receive the count value from the master counter wherein the calibration logic generates control signals to the RC oscillator to increase or decrease the RC time constant according to the value received in the count signal from the master counter.

2. A system of claim 1 wherein the register stores a reset number that is equal to 1,000.

3. The system of claim 1 wherein the calibration circuitry generates a signal to increase the RC time constant if the value of the count value received from the master counter is greater than 1,000.

4. The system of claim 1 wherein the calibration circuitry generates a signal to decrease the RC time constant if the value of the count value received from the master counter is less than 1,000.

5. The system of claim 1 wherein the calibration circuit includes logic to increase the RC time constant of the RC oscillator by generating signals to increase capacitance therein.

6. The system of claim 1 wherein the calibration circuit includes logic to decrease the RC time constant of the RC oscillator by generating signals to decrease capacitance therein.

7. The system of claim 1 wherein the RC time constant is adjusted by switching capacitors of a capacitor array in or out of connectivity within the RC oscillator according to whether an RC time constant requires increasing or decreasing to cause the oscillator to produce a desired frequency of operation.

8. A mothod for adjusting an RC time constant in an oscillator, comprising:

setting a capacitor array to an initial first value of capacitance;

receiving a count value;

determining whether the RC time constant is low;

if the RC time constant is low, incrementing the capacitance value to a new value;

if the RC time constant is not low, determining the whether the RC time constant is high;

if the RC time constant is high, decrementing the capacitance to a new value; and

determining if an amount of change of the capacitance value included a minimal step size.

9. The method of claim 8 wherein the new value is approximately one-half of the possible amount of capacitance that may be changed from a present value to a maximum value.

10. The method of claim 8 wherein the new value is a value that is approximately one-half of the possible amount of capacitance that may be changed from the present value to a minimum value.

11. The method of claim 8 wherein the RC time constant value is determined to be low if a count value is higher than a specified number.

12. The method of claim 8 wherein the RC time constant value is determined to be high if a count value is lower than a specified number.

13. The method of claim 8 wherein the initial value is one that is approximately half of the total amount of capacitance that may be set within the capacitor array.