Memory system with improved efficiency of data transfer between host, buffer and nonvolatile memory

• US 6,882,568 B2
• Filed: 04/02/2003
• Issued: 04/19/2005
• Est. Priority Date: 02/07/2002
• Status: Expired due to Term

• Current Assignee: Emergence Memory Solutions LLC
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nakamura, Yasuhiro, Hara, Fumio, Shiota, Shigemasa, Goto, Hiroyuki, Shibuya, Hirofumi
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/404,547
• Publication Number:
  US 20030202383A1
• Time in Patent Office: 748 Days
• Field of Search: 365/185.01, 365/185.08 A, 365/189.01, 365/189.05, 365/230.03, 365/233, 710/52, 710/53, 710/13, 710/66, 711/4, 711/100, 711/117, 711/118
• US Class Current: 365/185.08
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Claims

1. A nonvolatile memory system comprising:

a controller;

a buffer memory;

a nonvolatile memory;

a first signal line connected to the controller, for transferring data to/from the outside;

a second signal line connecting the controller to the buffer memory; and

a third signal line connecting the controller to the nonvolatile memory,

wherein said second signal line includes a clock signal line,

wherein said buffer memory is supplied a clock signal via said second signal line,

wherein a clock frequency of said clock signal is higher than a data transfer frequency of said third signal line, and

wherein a data transfer rate of said second signal line is equal to or higher than a sum of a data transfer rate of said first signal line and a data transfer rate of said third signal line.

2. The nonvolatile memory system according to claim 1,

wherein the data transfer rate of said first signal line is equal to or higher than the data transfer rate of said third signal line.

3. The nonvolatile memory system according to claim 2,

wherein said buffer memory is a memory to/from which data is input/output synchronously with said clock signal.

4. The nonvolatile memory system according to claim 3,

wherein in the case of storing data supplied from the outside into said nonvolatile memory, in said second signal line, transfer of data which is supplied from the outside and temporarily stored in the buffer memory and transfer of data which is temporarily stored in the buffer memory and is stored into said nonvolatile memory are performed in a time sharing manner.

5. The nonvolatile memory system according to claim 3,

wherein in the case of supplying data stored in said nonvolatile memory to the outside, in said second signal line, transfer of data which is read from said nonvolatile memory and temporarily stored in the buffer memory and transfer of data which is temporarily stored in the buffer memory and is supplied to the outside are performed in a time sharing manner.

6. The nonvolatile memory system according to claim 1,

further comprising a plurality of said nonvolatile memories, and a data transfer rate of said third signal line is equal to a sum of data transfer rates of said plurality of nonvolatile memories.

7. The nonvolatile memory system according to claim 6,

wherein the data transfer rate of said first signal line is equal to or higher than the data transfer rate of said third signal line.

8. The nonvolatile memory system according to claim 7,

wherein said buffer memory is a memory to/from which data is input/output synchronously with said clock signal.

9. The nonvolatile memory system according to claim 8,

wherein in the case of storing data supplied from the outside into said nonvolatile memory, in said second signal line, transfer of data which is supplied from the outside and temporarily stored into the buffer memory and transfer of data which is temporarily stored in the buffer memory and stored into any of said plurality of nonvolatile memories are performed in a time sharing manner.

10. The nonvolatile memory system according to claim 8,

wherein in the case of supplying data stored in said nonvolatile memory to the outside, in said second signal line, transfer of data which is read from any of said plurality of nonvolatile memories and temporarily stored into the buffer memory and transfer of data which is temporarily stored in the buffer memory and supplied to the outside are performed in a time sharing manner.