Readout circuit with gain and analog-to-digital a conversion for image sensor

• US 6,885,396 B1
• Filed: 03/08/1999
• Issued: 04/26/2005
• Est. Priority Date: 03/09/1998
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Barna, Sandor, Panicacci, Roger, Krymski, Alexander I., Mansoorian, Barmak
• Primary Examiner(s): Christensen, Andrew
• Assistant Examiner(s): TRAN, NHAN T
• Application Number:
  US09/264,501
• Time in Patent Office: 2,241 Days
• Field of Search: 348/241, 348/222.1, 348/302, 348/308, 348/294, 250/208.1, 341/120, 341/172, 341/150, 341/118, 341161- 3, 378/98.8
• US Class Current: 348/241
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A CMOS imager includes an array of active pixel sensors, wherein each pixel is associated with a respective column in the array. The imager also includes multiple circuits for reading out values of pixels from the active sensor array. Each readout circuit can be associated with a respective pair of columns in the array and can include first and second sample-and-hold circuits. The first and second sample-and-hold circuits are associated, respectively, with first and second columns of pixels in the array. Each readout circuit also includes an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit. The readout circuit also has an analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique. Use of the readout circuit can increase the parallel structure of the overall chip, thereby reducing the bandwidth which each readout circuit must be capable of handling.

Claims

1. A circuit for reading out values of pixels from an active pixel sensor array, the circuit comprising:

a first sample-and-hold circuit for sampling and storing signals from pixels in a first column;

a second sample-and-hold circuit for sampling and storing signals from pixels in a second column;

an operational amplifier-based charge sensing circuit, associated only with the first and second columns in the array, that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit; and

an analog-to-digital converter, associated only with the first and second columns in the array, for converting the differential output to a corresponding digital signal using a successive approximation technique, said analog-to-digital converter including a comparator and a first binary-scaled capacitor network;

wherein

the capacitors in the first network share a common node coupled to a first input of the comparator,

the amplified differential output signal from the charge sensing circuit is coupled to a second input of the comparator, and

each of the capacitors in the first capacitor network has an associated latch circuit for storing a bit corresponding to a differential signal for a pixel sampled by the first sample-and-hold circuit while a differential signal for a pixel sampled by the second sample-and-hold circuit is amplified and converted to a corresponding digital signal.

2. A circuit for reading out values of pixels from an active pixel sensor array, the circuit comprising:

a first sample-and-hold circuit for sampling and storing signals from pixels in a first column;

a second sample-and-hold circuit for sampling and storing signals from pixels in a second column;

an operational amplifier-based charge sensing circuit, associated only with the first and second columns in the array, that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit;

an analog-to-digital converter, associated only with the first and second columns in the array, for converting the differential output to a corresponding digital signal using a successive approximation technique, said analog-to-digital converter including a comparator and a first binary-scaled capacitor network; and

a calibration network including a second binary-scaled capacitor network used to successively approximate and store the offset of the comparator,

wherein

the capacitors in the first network share a common node coupled to a first input of the comparator,

the capacitors in the second capacitor network share a node in common with the capacitors in the first capacitor network,

the amplified differential output signal from the charge sensing circuit is coupled to a second input of the comparator, and

the calibration network selectively can be enabled to provide a DC shift to the common node to ensure that the signal for canceling the comparator offset appears as a positive voltage.

3. A circuit for reading out values of pixels from an active pixel sensor array, the circuit comprising:

a first sample-and-hold circuit for sampling and storing signals from pixels in a first column;

a second sample-and-hold circuit for sampling and storing signals from pixels in a second column;

an operational amplifier-based charge sensing circuit, associated only with the first and second columns in the array, that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit;

an analog-to-digital converter, associated only with the first and second columns in the array, for converting the differential output to a corresponding digital signal using a successive approximation technique, said analog-to-digital converter including a comparator and a first binary-scaled capacitor network; and

a calibration network including a second binary-scaled capacitor network used to successively approximate and store the offset of the comparator,

wherein

the capacitors in the first network share a common node coupled to a first input of the comparator,

the capacitors in the second capacitor network share a node in common with the capacitors in the first capacitor network,

the amplified differential output signal from the charge sensing circuit is coupled to a second input of the comparator, and

one side of each capacitor in the first capacitor network selectively can be connected to a first reference voltage, and wherein one side of each capacitor in the second capacitor network selectively can be connected to a second reference voltage different from the first reference voltage.

4. A CMOS imager comprising:

an array of active pixel sensors, wherein each pixel is associated with a respective column in the array; and

a plurality of readout circuits for reading out values of pixels from the active sensor array, wherein each readout circuit is associated with a respective pair of first and second columns in the array, and wherein each circuit includes;

a first sample-and-hold circuit for sampling and storing signals from pixels in the first column;

a second sample-and-hold circuit for sampling and storing signals from pixels in the second column;

an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit; and

an analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique, said

analog-to-digital converter including a comparator and a first binary-scaled capacitor network,

wherein

capacitors in the first network share a common node coupled to a first input of the comparator,

the amplified differential output signal from the charge sensing circuit is coupled to a second input of the comparator, and

each of the capacitors in the first capacitor network has an associated latch circuit for storing a bit corresponding to a differential signal for a pixel sampled by the first sample-and-hold circuit while a differential signal for a pixel sampled by the second sample-and-hold circuit is amplified and converted to a corresponding digital signal.

5. A CMOS imager comprising:

an array of active pixel sensors, wherein each pixel is associated with a respective column in the array; and

a plurality of readout circuits for reading out values of pixels from the active sensor array, wherein each readout circuit is associated with a respective pair of first and second columns in the array, and wherein each readout circuit includes;

a first sample-and-hold circuit for sampling and storing signals from pixels in the first column;

a second sample-and-hold circuit for sampling and storing signals from pixels in the second column;

an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit; and

analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique, said analog-to-digital converter including a comparator and a first binary-scaled capacitor network,

a calibration network for providing a signal to cancel an offset of the comparator, said calibration network including a second binary-scaled capacitor network used to successively approximate and store the offset of the comparator,

wherein

capacitors in the first network share a common node coupled to a first input of the comparator,

the amplified differential output signal from the charge sensing circuit is coupled to a second input of the comparator,

the capacitors in the second capacitor network share a node in common with the capacitors in the first capacitor network, and

the calibration network selectively can be enabled to provide a voltage shift to the common node to ensure that the signal for canceling the comparator offset appears as a positive voltage.

6. A CMOS imager comprising:

an array of active pixel sensors, wherein each pixel is associated with a respective column in the array; and

a plurality of readout circuits for reading out values of pixels from the active sensor array, wherein each readout circuit is associated with a respective pair of first and second columns in the array, and wherein each readout circuit includes;

a first sample-and-hold circuit for sampling and storing signals from pixels in the first column;

a second sample-and-hold circuit for sampling and storing signals from pixels in the second column;

an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit; and

an analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique, said analog-to-digital converter including a comparator and a first binary-scaled capacitor network,

a calibration network for providing a signal to cancel an offset of the comparator, said calibration network including a second binary-scaled capacitor network used to successively approximate and store the offset of the comparator,

wherein

capacitors in the first network share a common node coupled to a first input of the comparator,

the amplified differential output signal from the charge sensing circuit is coupled to a second input of the comparator,

the capacitors in the second capacitor network share a node in common with the capacitors in the first capacitor network, and

one side of each capacitor in the first capacitor network selectively can be connected to a first reference voltage, and wherein one side of each capacitor in the second capacitor network selectively can be connected to a second reference voltage different from the first reference voltage.

7. A CMOS imager comprising:

an array of active pixel sensors, wherein each pixel is associated with a respective column in the array; and

a plurality of readout circuits for reading out values of pixels from the active sensor array, wherein each readout circuit is associated with a respective pair of first and second columns in the array, and wherein each readout circuit includes;

a first sample-and-hold circuit for sampling and storing signals from pixels in the first column;

a second sample-and-hold circuit for sampling and storing signals from pixels in the second column;

an operational amplifier-based charge sensing circuit that selectively provides an amplified differential output signal based on signals sampled either by the first sample-and-hold circuit or the second sample-and-hold circuit; and

an analog-to-digital converter for converting the differential output to a corresponding digital signal using a successive approximation technique, said analogs-to-digital converter including a comparator and a first binary-scaled capacitor network,

a calibration network for providing a signal to cancel an offset of the comparator, said calibration network including a second binary-scaled capacitor network used to successively approximate and store the offset of the comparator,

wherein

capacitors in the first network share a common node coupled to a first input of the comparator,

the amplified differential output signal from the charge sensing circuit is coupled to a second input of the comparator,

the capacitors in the second capacitor network share a node in common with the capacitors in the first capacitor network, and

the calibration network selectively can be enabled to provide a post-gain offset for the differential output signal from the charge sensing circuit.