One transistor SOI non-volatile random access memory cell

• US 6,888,200 B2
• Filed: 04/29/2003
• Issued: 05/03/2005
• Est. Priority Date: 08/30/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US10/425,483
• Publication Number:
  US 20040041206A1
• Time in Patent Office: 735 Days
• Field of Search: 257347-349, 257351-354, 257/390, 257/391
• US Class Current: 257/348
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Claims

1. A semiconductor structure, comprising:

a substrate;

a buried insulator layer positioned over at least a portion of the substrate;

a body region positioned over the buried insulator layer, the body region including a charge trapping region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

2. The structure of claim 1, wherein the charge trapping region includes silicon nitride (Si₃N₄).

3. The structure of claim 1, wherein the charge trapping region includes an oxynitride.

4. The structure of claim 1, wherein the charge trapping region includes a metal oxide.

5. The structure of claim 4, wherein the metal oxide includes a transition metal oxide.

6. The structure of claim 1, wherein the charge trapping region includes a metal silicide.

7. The structure of claim 1, wherein the charge trapping region includes a charge trapping layer located at or near an interface between the body region and the buried insulator layer.

8. The structure of claim 1, wherein the body region has a number of sidewalls, and the charge trapping region includes a sidewall charge trapping layer located at or near at least a portion of at least one of the number of sidewalls.

9. A semiconductor structure, comprising:

a substrate;

a buried insulator layer positioned over at least a portion of the substrate;

a body region positioned over the buried insulator layer;

a charge trapping region formed at an interface between the buried insulator layer and the body region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

10. The structure of claim 9, wherein the charge trapping region includes silicon nitride (Si₃N₄).

11. The structure of claim 9, wherein the charge trapping region includes an oxynitride.

12. The structure of claim 11, wherein the oxynitride has a refractive index within a range of approximately 1.75 to approximately 1.9.

13. The structure of claim 9, wherein the body region has a number of sidewalls, and the charge trapping region is further formed at or near at least a portion of at least one of the number of sidewalls.

14. A semiconductor structure, comprising:

a substrate;

a buried insulator layer positioned over at least a portion of the substrate;

a body region positioned over the buried insulator layer;

a charge trapping region formed in the body region near an interface between the buried insulator layer and the body region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

15. The structure of claim 14, wherein the charge trapping region includes silicon nitride (Si₃N₄).

16. The structure of claim 14, wherein the charge trapping region includes an oxynitride.

17. The structure of claim 16, wherein the oxynitride has a refractive index within a range of approximately 1.75 to approximately 1.9.

18. The structure of claim 14, wherein the body region has a number of sidewalls, and the charge trapping region is further formed at or near at least a portion of at least one of the number of sidewalls.

19. A semiconductor structure, comprising:

a substrate;

a buried insulator layer positioned over at least a portion of the substrate;

a body region positioned over the buried insulator layer, the body region including a charge trapping oxynitride region, the oxynitride region having a refractive index within a range of approximately 1.75 to approximately 1.9;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

20. The structure of claim 19, wherein the oxynitride region is positioned over an interface between the body region and the buried insulator layer.

21. The structure of claim 19, wherein the oxynitride region is positioned at an interface between the body region and the buried insulator layer.

22. A semiconductor structure, comprising:

a substrate;

a buried insulator layer positioned over at least a portion of the substrate;

a body region positioned over the buried insulator layer, the body region including a charge trapping composite;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

23. The structure of claim 22, wherein the charge trapping composite includes oxide-nitride.

24. The structure of claim 22, wherein the charge trapping composite includes oxide-alumina.

25. The structure of claim 22, wherein the charge trapping region includes a charge trapping layer located at or near an interface between the body region and the buried insulator layer.

26. The structure of claim 22, wherein the body region has a number of sidewalls, and the charge trapping region includes a sidewall charge trapping layer located at or near at least a portion of at least one of the number of sidewalls.

27. A semiconductor structure, comprising:

a substrate;

a buried insulator layer positioned over at least a portion of the substrate;

a body region positioned over the buried insulator layer, the body region including a charge trapping laminate;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

28. The structure of claim 27, wherein the charge trapping laminate includes oxide-nitride.

29. The structure of claim 27, wherein the charge trapping laminate includes oxide-alumina.

30. The structure of claim 27, wherein the charge trapping region includes a charge trapping layer located at or near an interface between the body region and the buried insulator layer.

31. The structure of claim 27, wherein the body region has a number of sidewalls, and the charge trapping region includes a sidewall charge trapping layer located at or near at least a portion of at least one of the number of sidewalls.

32. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region, including a charge trapping region within the floating body region, the charge trapping region including silicon nitride (Si₃N₄);

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

33. The memory cell of claim 32, wherein the transistor is a partially-depleted SOI field effect transistor (PD-SOI-FET).

34. The memory cell of claim 32, wherein the transistor is a fully-depleted SOI field effect transistor (FD-SOI-FET).

35. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region, including a charge trapping region within the floating body region, the charge trapping region including an oxynitride;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

36. The memory cell of claim 35, wherein the transistor is a partially-depleted SOI field effect transistor (PD-SOI-FET).

37. The memory cell of claim 35, wherein the transistor is a fully-depleted SOI field effect transistor (FD-SOI-FET).

38. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region, including a charge trapping region within the floating body region, the charge trapping region including a metal oxide;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

39. The memory cell of claim 38, wherein the metal oxide includes a transition metal oxide.

40. The memory cell of claim 38, wherein the transistor is a partially-depleted SOI field effect transistor (PD-SOI-FET).

41. The memory cell of claim 38, wherein the transistor is a fully-depleted SOI field effect transistor (FD-SOI-FET).

42. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region, including a charge trapping region within the floating body region, the charge trapping region including a metal silicide;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

43. The memory cell of claim 42, wherein the transistor is a partially-depleted SOI field effect transistor (PD-SOI-FET).

44. The memory cell of claim 42, wherein the transistor is a fully-depleted SOI field effect transistor (FD-SOI-FET).

45. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region, including a charge trapping composite within the floating body region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

46. The memory cell of claim 45, wherein the charge trapping composite includes oxide-nitride.

47. The memory cell of claim 45, wherein the charge trapping composite includes oxide-alumina.

48. The memory cell of claim 45, wherein the transistor is a partially-depleted SOI field effect transistor (PD-SOI-FET).

49. The memory cell of claim 45, wherein the transistor is a fully-depleted SOI field effect transistor (FD-SOI-FET).

50. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region, including a charge trapping laminate within the floating body region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

51. The memory cell of claim 50, wherein the charge trapping laminate includes oxide-nitride.

52. The memory cell of claim 50, wherein the charge trapping laminate includes oxide-alumina.

53. The memory cell of claim 50, wherein the transistor is a partially-depleted SOI field effect transistor (PD-SOI-FET).

54. The memory cell of claim 50, wherein the transistor is a fully-depleted SOI field effect transistor (FD-SOI-FET).

55. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region having a number of sidewalls, the floating body region including a sidewall charge trapping region at or near at least a portion of at least one of the number of sidewalls;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

56. The memory cell of claim 55, wherein the floating body region further includes a charge trapping layer at or near at least a portion of an interface between the buried insulator region and the floating body region.

57. The memory cell of claim 55, wherein the transistor is a partially-depleted SOI field effect transistor (PD-SOI-FET).

58. The memory cell of claim 55, wherein the transistor is a fully-depleted SOI field effect transistor (FD-SOI-FET).

59. A method of forming a non-volatile memory cell, comprising:

forming a body region over a buried oxide (BOX) insulator on a substrate;

forming a charge trapping region in the body region;

forming a first diffusion region and a second diffusion region to define a channel region in the body region;

forming a gate dielectric over the channel region; and

forming a gate over the gate dielectric.

60. The method of claim 59, wherein forming a charge trapping region in the body region includes forming the charge trapping region at an interface between the BOX insulator and the body region.

61. The method of claim 59, wherein forming a charge trapping region in the body region includes forming the charge trapping region over an interface between the BOX insulator and the body region.

62. The method of claim 59, wherein forming a charge trapping region in the body region includes forming the charge trapping region along a portion of at least one sidewall of the body region.

63. The method of claim 59, wherein forming a charge trapping region in the body region includes incorporating nitrogen in the charge trapping region.

64. The method of claim 63, wherein forming a charge trapping region in the body region further includes incorporating oxygen to form an oxynitride region.

65. The method of claim 63, wherein incorporating oxygen to form an oxynitride region includes forming an oxynitride region with a refractive index within a range of approximately 1.75 to 1.9.

66. The method of claim 59, wherein forming a charge trapping region in the body region includes forming a metal oxide.

67. The method of claim 66, wherein forming a metal oxide includes forming a transition metal oxide.

68. The method of claim 59, wherein forming a charge trapping region in the body region includes forming a metal silicide.

69. The method of claim 59, wherein forming a charge trapping region in the body region includes forming an oxide-nitride composite.

70. The method of claim 59, wherein forming a charge trapping region in the body region includes forming an oxide-nitride laminate.

71. The method of claim 59, wherein forming a charge trapping region in the body region includes forming an oxide-alumina composite.

72. The method of claim 59, wherein forming a charge trapping region in the body region includes forming an oxide-alumina laminate.

73. A method of forming a non-volatile memory cell, comprising:

forming a body region over a buried oxide (BOX) insulator on a substrate;

forming a charge trapping silicon nitride (Si₃N₄) region in the body region;

forming a first diffusion region and a second diffusion region to define a channel region in the body region;

forming a gate dielectric over the channel region; and

forming a gate over the gate dielectric.

74. The method of claim 73, wherein forming a silicon nitride (Si₃N₄) includes a process selected from a group consisting of:

thermal recombination, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and ion implantation.

75. The method of claim 73, wherein forming a silicon nitride (Si₃N₄) includes incorporating nitrogen into a silicon body region to form the silicon nitride (Si₃N₄).

76. A method of forming a non-volatile memory cell, comprising:

forming a body region over a buried oxide (BOX) insulator on a substrate;

forming a charge trapping oxynitride region in the body region;

forming a first diffusion region and a second diffusion region to define a channel region in the body region;

forming a gate dielectric over the channel region; and

forming a gate over the gate dielectric.

77. The method of claim 76, wherein forming the oxynitride region includes forming a silicon nitride (Si₃N₄) region, and incorporating oxygen into the silicon nitride (Si₃N₄) region.

78. The method of claim 76, wherein forming the oxynitride region includes forming a stoichiometric silicon dioxide (SiO₂) region, and incorporating nitrogen into the silicon dioxide (SiO₂) region.

79. The method of claim 76, wherein forming the oxynitride region includes incorporating nitrogen into a silicon dioxide (SiO₂) BOX region.

80. The method of claim 76, wherein forming a charge trapping oxynitride region includes forming an oxynitride region with a refractive index within a range of about 1.75 to about 1.9.

81. The method of claim 76, wherein forming a charge trapping oxynitride region include adjusting an oxygen concentration for the oxynitride region to provide a desired charge trapping probability and a desired charge trap depth.

82. The method of claim 76, wherein forming a charge trapping oxynitride region in the body region includes combining appropriate reactive sources of silicon, oxygen and nitrogen.

83. The method of claim 76, wherein forming a charge trapping oxynitride region in the body region includes incorporating nitrogen and oxygen into silicon.