High speed peak amplitude comparator

• US 6,888,381 B2
• Filed: 10/01/2001
• Issued: 05/03/2005
• Est. Priority Date: 10/01/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Momtaz, Afshin, Hairapetian, Armond, Tan, Wee-Guan
• Primary Examiner(s): Nguyen, Linh M.
• Application Number:
  US09/969,837
• Publication Number:
  US 20030062928A1
• Time in Patent Office: 1,310 Days
• Field of Search: 327/58, 327/62, 327/63, 327/65, 327/71, 327/77, 327/79, 327/78, 327/80, 330/253, 330/252, 330/277
• US Class Current: 327/58
• CPC Class Codes: G01R 19/04 Measuring peak values or amplitude or envelope of ac or of pulses
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02

Abstract

Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

Claims

1. A peak amplitude comparator comprising:

an input circuit having an input terminal coupled to receive an input signal, and configured to store a first signal with an amplitude that is substantially equal to a peak amplitude of the input signal minus a predetermined voltage drop and to generate the stored first signal at an output terminal;

a reference circuit having an input terminal coupled to receive a reference voltage and configured to generate at an output terminal a second signal with an amplitude that is substantially equal to the reference voltage minus the predetermined voltage drop; and

a comparator having a first terminal coupled to receive the first signal and a second terminal coupled to receive the second signal.

2. The peak amplitude comparator of claim 1 wherein the comparator is configured to compare a magnitude of the first signal to a magnitude of the second signal.

3. The peak amplitude comparator of claim 2 wherein the predetermined voltage drop is substantially equal to a transistor threshold voltage.

4. The peak amplitude comparator of claim 3 wherein the input circuit comprises:

a first transistor having a gate terminal coupled to receive the input signal, a first source/drain terminal coupled to a logic high power supply and a second source/drain terminal coupled to the output terminal of the input circuit;

a capacitor coupled to the second source/drain terminal of the first transistor; and

a current source coupled to the second source/drain terminal of the first transistor, wherein the predetermined voltage drop is substantially equal to a threshold Voltage of the first transistor.

5. The peak amplitude comparator of claim 4 wherein the reference circuit comprises:

a second transistor having a gate terminal coupled to receive the reference signal, a first source/drain terminal coupled to the logic high power supply and a second source/drain terminal coupled to the output terminal of the reference circuit; and

a current source coupled to the second source/drain terminal of the second transistor.

6. The peak amplitude comparator of claim 1 wherein the input signal comprises first and second differential signals and the input terminal comprises first and second terminals coupled to respectively receive the first and second differential signals.

7. The peak amplitude comparator of claim 6 wherein the input circuit comprises:

a first transistor having a gate terminal coupled to receive the first differential signal, a first source/drain terminal coupled to a logic high power supply and a second source/drain terminal coupled to the output terminal of the input circuit;

a second transistor having a gate terminal coupled to receive the second differential signal, a first source/drain terminal coupled to the logic high power supply and a second source/drain terminal coupled to the output terminal of the input circuit;

a capacitor coupled to the second source/drain terminals of the first and second transistors; and

a current source coupled to the second source/drain terminals of the first and second transistors.

8. The peak amplitude comparator of claim 7 wherein the predetermined voltage drop is substantially equal to a threshold voltage of the first transistor.

9. A differential peak amplitude comparator comprising:

an input circuit having first and second input terminals coupled to respectively receive differential first and second input signals, and configured to generate at an output terminal a first signal with an amplitude that is substantially equal to a peak amplitude of either of the first and second input signals minus a predetermined voltage drop;

a reference circuit having an input terminal coupled to receive a reference voltage and configured to generate at an output terminal a second signal with an amplitude that is substantially equal to the reference voltage minus the predetermined voltage drop; and

a comparator having a first terminal coupled to receive the first signal and a second terminal coupled to receive the second signal.

10. The differential peak amplitude comparator of claim 9 wherein the input circuit comprises:

a first transistor having a gate terminal coupled to receive the first input signal, a first source/drain terminal coupled to a logic high power supply and a second source/drain terminal coupled to the output terminal of the input circuit;

a second transistor having a gate terminal coupled to receive the second input signal, a first source/drain terminal coupled to the logic high power supply and a second source/drain terminal coupled to the output terminal of the input circuit;

a capacitor coupled to the second source/drain terminals of the first and second transistors; and

a current source coupled to the second source/drain terminals of the first and second transistors.

11. The differential peak amplitude comparator of claim 10, wherein the predetermined voltage drop is substantially equal to a threshold voltage of the first transistor.

12. A method for comparing a peak amplitude of an input signal to a reference voltage, comprising:

storing, on a first node, a first signal having an amplitude that is substantially equal to a peak amplitude of the input signal minus a predetermined voltage drop;

generating a second signal having an amplitude that is substantially equal to the reference voltage minus the predetermined voltage drop; and

comparing a magnitude of the first signal to a magnitude of the second signal.

13. The method of claim 12 wherein the step of storing comprises:

turning on a switch to charge a capacitor when the input signal increases in amplitude; and

turning off the switch when the input signal starts to decrease.

14. The method of claim 13 wherein the steps of turning on and turning off the switch comprise directly applying the input signal to a control terminal of the switch.