Active matrix substrate and manufacturing method therefor

• US 6,891,196 B2
• Filed: 07/11/2003
• Issued: 05/10/2005
• Est. Priority Date: 10/26/1999
• Status: Expired due to Term

• Current Assignee: Vista Peak Ventures LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: NEC LCD Technologies Limited (NEC Corporation)
• Inventors: Kanou, Hiroshi, Yoshikawa, Tae, Hayase, Takasuke, Ihida, Satoshi, Sakamoto, Michiaki, Kaneko, Wakahiko, Yamaguchi, Hirotaka, Tanaka, Hiroaki
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US10/617,035
• Publication Number:
  US 20040084672A1
• Time in Patent Office: 669 Days
• Field of Search: 257/72, 257/435, 349/42, 349/110, 438/155
• US Class Current: 257/72
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode is isolated in each layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer and a TFF area. A drain electrode layer is formed by a first passivation film with the first passivation film formed as an upper layer. In a second passivation film, formed above the first passivation film, are bored a first opening through the first and second passivation films and a second opening through the second passivation film. A wiring connection layer is formed by ITO provided as an uppermost layer. A storage capacitance unit, including the first and second passivation films sandwiched between the gate electrode and an electrode layer formed as a co-layer with respect to the gate electrode, is connected to the pixel electrode.

Claims

1. A lateral electrical field type active matrix substrate comprising:

(a) a gate electrode layer, a gate insulating layer and an amorphous silicon semiconductor layer deposited in a substantially stacked fashion on a transparent insulating substrate, viewed from a direction normal to said transparent insulating substrate, to form a layered structure, including a gate electrode, a gate wiring, a comb-shaped common electrode and a thin-film transistor area;

(b) a drain wiring formed on a first passivation film disposed on said substrate so as to cover said layered structure; and

(c) a second passivation film formed as a layer overlying said drain wiring and said first passivation film;

(d) source/drain openings passing through said first passivation film and said second passivation film to reach said amorphous silicon semiconductor layer, and

(e) an opening passing through said second passivation film to reach said drain wiring;

wherein

(f) a wiring layer extending through said drain opening to said drain wiring and a pixel electrode connected to said source opening are formed by a pixel electrode film disposed on said second passivation film.

3. The active matrix substrate as defined in claim 1

wherein

said second passivation film has a substantially flattened surface, and wherein

said pixel electrode film is formed on said flattened surface.

5. The active matrix substrate as defined in claim 1

wherein said second passivation film comprises a material having a high etching selectivity with respect to said amorphous silicon semiconductor layer and to said gate insulating layer.

10. The active matrix substrate as defined in claim 1 wherein

a n⁺layer doped with phosphorus is formed on a surface layer of an amorphous silicon semiconductor layer exposed by said opening, and wherein

said drain wiring or said pixel electrode is connected via said n⁺layer to said amorphous silicon semiconductor layer.

23. A liquid crystal display device comprising the active matrix substrate as defined in claim 1.

2. A lateral electrical field type active matrix substrate comprising:

(a) a gate electrode layer, a gate insulating layer and an amorphous silicon semiconductor layer deposited in a substantially stacked fashion on a transparent insulating substrate, viewed from a direction normal to said transparent insulating substrate, to form a layered structure, including a gate electrode, a gate wiring, a comb-shaped common electrode and a thin-film transistor area;

(b) a drain wiring formed on a first passivation film disposed on said substrate so as to cover said layered structure; and

(c) a second passivation film formed as a layer overlying said drain wiring and said first passivation film;

(d) source/drain openings passing through said first passivation film and said second passivation film to reach said amorphous silicon semiconductor layer, and

(e) an opening passing through said second passivation film to reach said drain wiring;

wherein

(f) a wiring layer extending through said drain opening to said drain wiring and a pixel electrode connected to said source opening are formed by a pixel electrode film, and

wherein

(g) said pixel electrode film is formed in a comb-shape on said first passivation film above said common electrode and is covered by said second passivation film.

4. The active matrix substrate as defined in claim 2

wherein

said second passivation film has a substantially flattened surface, and wherein

said pixel electrode film is formed on said flattened surface.

6. The active matrix substrate as defined in claim 2

wherein said second passivation film comprises a material having a high etching selectivity with respect to said amorphous silicon semiconductor layer and to said gate insulating layer.

11. The active matrix substrate as defined in claim 2 wherein a n⁺layer doped with phosphorous is formed on a surface layer of an amorphous silicon semiconductor layer exposed by said opening, and wherein

said drain wiring or said pixel electrode is connected via said n⁺layer to said amorphous silicon semiconductor layer.

24. A liquid crystal display device comprising the active matrix substrate as defined in claim 2.

7. An active matrix substrate comprising:

(a) a gate electrode layer, a gate insulating film and an amorphous silicon semiconductor layer deposited in a substantially stacked fashion on an insulating substrate, viewed from a direction normal to said insulating substrate, to form a layered structure, including a gate electrode, a gate wiring and a thin-film transistor area;

(b) a drain wiring formed on a passivation film covering said layered structure and said gate wiring;

(c) a black matrix formed on said passivation film at an area above said gate wiring, said layered structure and the drain wiring;

(d) a color layer or layers formed in a region surrounded by said black matrix;

(e) a planarized film formed to cover said passivation film and said black matrix; and

(f) source/drain openings passing through said passivation film and said planarized film to reach said amorphous silicon layer, and an opening passing through said black matrix and said planarized film to reach said drain wiring; and

(g) a wiring layer connecting to said drain wiring layer through said drain opening by a pixel electrode film disposed on said planarized film.

8. The active matrix substrate as defined in claim 7 wherein

a pixel electrode connecting to said source opening is disposed by said pixel electrode film;

a capacitance electrode layer is disposed on said passivation film lying on said gate wiring; and

wherein

said capacitance electrode layer is connected to said pixel electrode through openings formed in said black matrix and the planarized film.

9. The active matrix substrate as defined in claim 7 wherein

said pixel electrode is branched from said gate wiring.

12. A method for producing an active matrix substrate comprising:

(a) layering a gate electrode layer, a gate insulating film and an a-Si layer in this order on a transparent insulating substrate and forming a gate electrode, a gate wiring and a thin-film transistor area, using a first mask;

(b) depositing a first passivation film and a drain electrode layer on said gate electrode, and removing said drain electrode layer lying in a preset area, using a second mask, to form a drain wiring;

(c) depositing a second passivation film above said drain wiring, forming openings, using a third mask, at preset positions in said amorphous silicon semiconductor layer passing through said first and second passivation films for connection to source/drain electrodes as well as forming an opening, above said drain wiring, passing through said second passivation film; and

(d) depositing a transparent electrode layer as an overlying layer on said second passivation film and on and within said openings, to form a drain wiring connection connecting to an amorphous silicon layer exposed in said opening for said drain electrode, using a fourth mask, and to connect the amorphous silicon layer exposed in said opening for said source electrode to a pixel electrode comprised of said transparent electrode layer.

15. The method for producing an active matrix substrate as defined in claim 12 further comprising:

substantially planarizing the surface of said second passivation film after step (c) and before step (d);

forming said transparent electrode layer in step (d) on the surface of said second passivation film.

16. The method for producing an active matrix substrate as defined in claim 12 wherein, in step (a), said gate insulating film and the amorphous silicon layer on said gate wiring are selectively removed, leaving said gate insulating film and the amorphous silicon layer on said gate electrode.

20. The method for producing an active matrix substrate as defined in claim 12 further comprising:

forming an ohmic contact layer within said openings as an overlying layer, following step (c) of forming the opening in said passivation film and before step (d) of forming said transparent electrode layer;

said transparent electrode layer being connected to said ohmic contact layer.

21. The method for producing an active matrix substrate as defined in claim 12 wherein

said second passivation film comprises a material having a high etching selectivity with respect to said amorphous silicon semiconductor layer and the gate insulating film.

22. The method for producing an active matrix substrate as defined in claim 12,

wherein said second passivation film comprises one of a silicon oxide film and a composite laminate layer of a silicon oxide film and an organic inter-layer film.

13. A method for producing an active matrix substrate comprising:

(a) layering a gate electrode layer, a gate insulating film and an a-Si layer in this order on a transparent insulating substrate to form a gate electrode, a gate wiring connection and a thin-film transistor area, using a first mask;

(b) depositing a first passivation film and a drain electrode layer on said gate electrode and removing said drain electrode metal layer lying in a preset area, using a second mask, to form a drain wiring and a storage capacitance electrode;

(c) depositing a second passivation film as an overlying layer of said drain wiring, forming openings, using a third mask, at preset positions in said amorphous silicon semiconductor layer passing through said first and second passivation films for connection to source/drain electrodes, an opening above said drain wiring, passing through said second passivation film, and an opening for connection to said storage capacitance electrode; and

(d) depositing a transparent electrode layer as an overlying layer on said second passivation film and on and within said openings, to form a drain wiring connection connecting to an amorphous silicon layer exposed in an opening for said drain electrode, and a wiring connection for connection to said storage capacitance electrode, using a fourth mask, and connecting the amorphous silicon layer exposed in said opening for said source electrode to a pixel electrode comprised of said transparent electrode layer.

14. A method for producing an active matrix substrate comprising:

(a) layering a gate electrode layer, a gate insulating film and an a-Si layer in this order on a transparent insulating substrate and forming a gate electrode, a gate wiring, a common electrode and a thin-film transistor area, using a first mask;

(b) depositing a first passivation film and a drain electrode layer on said gate electrode and removing said drain electrode layer lying in a preset area, using a second mask, to form a drain wiring and pixel electrodes;

(c) depositing a second passivation film as an overlying layer on said drain wiring, forming openings, using a third mask, at preset positions in said amorphous silicon semiconductor layer passing through said first and second passivation films for connection to source/drain electrodes, and an opening, above said drain wiring, passing through said second passivation film; and

(d) depositing a transparent electrode layer as an overlying layer on said second passivation film and on said openings, to form a drain wiring connection connecting to an amorphous silicon layer exposed in an opening for said drain electrode, using a fourth mask, and connecting the amorphous silicon layer exposed in said opening for said source electrode to a pixel electrode comprised of said transparent electrode layer.

17. A method for producing an active matrix substrate comprising:

(a) layering a gate electrode layer, a gate insulating film and an amorphous silicon layer in this sequence on an insulating substrate to form a gate electrode, a gate wiring and a thin film transistor area, using a first mask;

(b) depositing a passivation film and a drain electrode layer on said gate electrode and removing said drain electrode layer in a pre-set region, using a second mask, to form a drain wiring;

(c) forming a black matrix on said passivation film over said gate wiring and said drain wiring, and forming a color layer in a region surrounded by said black matrix on said passivation film;

(d) forming a planarized film covering said black matrix and the color layer;

(e) forming openings at pre-set positions in said amorphous silicon layer passing through said passivation film, black matrix and the planarized film, using a third mask, for connection to source/drain electrodes, and also forming an opening, above said drain wiring, passing through said black matrix and said planarized film; and

(f) depositing a transparent electrode layer as an upper layer of said planarized film and said opening, forming a drain wiring connection connecting to a amorphous silicon layer exposed in an opening part of said drain electrode, using a fourth mask, and connecting the amorphous silicon layer exposed in an opening for said source electrode to a pixel electrode formed by said transparent electrode layer.

18. The method for producing an active matrix substrate as defined in claim 17 wherein,

in step (b), a storage capacitance electrode is formed on said passivation film lying on said gate wiring, simultaneously with formation of said drain wiring;

in step (e), an opening is formed passing through said black matrix and said planarized film above said capacitance electrode film, using a third mask; and

in step (f), said capacitance electrode film exposed to said opening and the pixel electrode made up of the transparent electrode layer are connected, using said fourth mask.

19. The method for producing an active matrix substrate as defined in claim 17, further comprising forming at least one color layer using at least one additional mask.