Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell

• US 6,891,223 B2
• Filed: 03/19/2003
• Issued: 05/10/2005
• Est. Priority Date: 03/19/2002
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz, Rieger, Walter, Krumrey, Joachim, Henninger, Ralf, Pölzl, Martin
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US10/392,025
• Publication Number:
  US 20030222297A1
• Time in Patent Office: 783 Days
• Field of Search: 257/330, 257/331, 257/340, 257/341, 257/386
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.

Claims

1. A transistor configuration, comprising:

at least one gate terminal;

at least one source terminal;

at least one drain terminal;

a semiconductor substrate having a substrate surface;

at least one active cell array formed in said semiconductor substrate, said semiconductor substrate having at least one trench formed therein within said active cell array

an edge region adjoining said active cell array and said trench extending into said edge region;

at least one trench transistor cell formed along said trench;

at least two electrode structures disposed within said trench and extending along said trench; and

metallizations disposed substantially above said substrate surface of said semiconductor substrate, at least one of said two electrode structures electrically conductively connected to one of said metallizations in said edge region.

2. The transistor configuration according to claim 1, further comprising an insulation disposed in said trench, said at least two electrode structures include a first electrode structure and a second electrode structure disposed in said trench, said electrode structures are disposed at least one of besides one another and one above the other and are electrically insulated from one another and from said semiconductor substrate by said insulation, said electrode structures are each electrically conductively connected to a corresponding one of said metallizations.

3. The transistor configuration according to claim 2, wherein:

said trench is one of a plurality of trenches formed in said semiconductor substrate;

said trench transistor cell is one of a plurality of trench transistor cells disposed in said trenches, in each said trench, said first electrode structure is a gate electrode and said second electrode structure is a field electrode, said field electrode substantially disposed below said gate electrode.

4. The transistor configuration according to claim 1, wherein the transistor configuration is a trench MOS power transistor, said metallizations include at least one gate metallization electrically conductively connected to said gate terminal, a source metallization electrically conductively connected to said source terminal, and a drain metallization electrically conductively connected to said drain terminal, said gate metallization at least partly surrounding said source metallization which is substantially disposed above said active cell array.

5. The transistor configuration according to claim 1, wherein:

said semiconductor substrate has transverse trenches formed therein, said gate electrode of each of said trench transistor cells of said active cell array are electrically conductively connected to one another through said transverse trenches;

said trenches have first sections and second sections; and

one of said metallizations is a field metallization, and at least one part of said field metallization is disposed in said edge region above said first section of said trenches, said field metallization having at least one plated-through hole electrically conductively connecting said field electrode to said field metallization.

6. The transistor configuration according to claim 1, wherein another one of said metallizations is a gate metallization, at least one part of said gate metallization is disposed in said edge region above said second section of said trenches and has at least one further plated through hole electrically conductively connecting said gate electrode to said gate metallization.

7. The transistor configuration according to claim 1, wherein said gate electrode extends out into said edge region and into said second sections over said substrate surface and forms a gate structure above said substrate surface, and at least one part of said gate metallization is disposed in said edge region section by section above said gate structure and is electrically conductively connected to said gate structure by a plurality of said further plated-through hole.

8. The transistor configuration according to claim 1, wherein:

said trench has a first section and a second section; and

one of said two electrode structures is a field electrode extending into said edge region and into said first section over said substrate surface and forms a field structure above said substrate surface; and

one of said metallizations is a field metallization and at least one part of said field metallization is disposed in said edge region section by section above said field structure and has a plurality of plated-through holes electrically conductively connecting said field structure to said field metallization.

9. The transistor configuration according to claim 8, wherein:

one of said two electrode structures is a gate electrode; and

another one of said metallizations is a gate metallization and at least one part of said gate metallization is disposed in said edge region above said second section of said trench, said gate metallization has at least one further plated-through hole electrically conductively connecting said gate electrode to said gate metallization.

10. The transistor configuration according to claim 8, wherein:

one of said electrode structures is a gate electrode extending out into said edge region and into said second section over said substrate surface (7) and forms a gate structure above said substrate surface; and

another one of said metallizations is a gate metallization and at least one part of said gate metallization is disposed in said edge region section by section above said gate structure, said gate metallization having a plurality of further plated-through holes electrically conductively connecting said gate structure to said gate metallization.

11. The transistor configuration according to claim 10, wherein said field structure is one of a plurality of field structures, said gate structure and said field structures are fashioned exclusively in a common plane, said gate structure at least partly surrounding said field structures.

12. The transistor configuration according to claim 10, wherein said field structure is one of a plurality of field structures, said field structures are covered at least in sections by said gate structure in a second layer.

13. The transistor configuration according to claim 1, further comprising a field terminal electrically conductively connected to one of said metallizations being a field metallization.

14. The transistor configuration according to claim 1, wherein said field metallization is a source metallization.

15. The transistor configuration according to claim 1, wherein said gate electrode and said gate structure emerged from an identical layer.

16. The transistor configuration according to claim 1, wherein said field electrode and said field structure emerged from an identical layer.