Capped dual metal gate transistors for CMOS process and method for making the same

  • US 6,894,353 B2
  • Filed: 07/31/2002
  • Issued: 05/17/2005
  • Est. Priority Date: 07/31/2002
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a semiconductor substrate having a first well and a second well, wherein the first well has a first conductivity type and the second well has a second conductivity type different than the first conductivity type;

    a gate dielectric over at least a portion of a first well and a portion of a second well;

    a first gate over the first well and the gate dielectric and comprising a titanium nitride layer, a first tantalum silicon nitride layer, and a first conductive silicon-containing layer, wherein the titanium nitride layer is in physical contact with the gate dielectric; and

    a second gaze over the second well and the gate dielectric and comprising a tantalum silicon nitride layer and a conductive silicon-containing layer, wherein the tantalum silicon nitride layer of the second gate is in physical contact with the gate dielectric.

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