Method for testing a device and a test configuration including a device with a test memory

• US 6,895,538 B2
• Filed: 07/18/2001
• Issued: 05/17/2005
• Est. Priority Date: 07/18/2000
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Hartmann, Henning, Ruf, Wolfgang, Düregger, Reinhard, Benedix, Alexander
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Britt, Cynthia
• Application Number:
  US09/907,694
• Publication Number:
  US 20040015313A1
• Time in Patent Office: 1,399 Days
• Field of Search: 714/718, 714/723, 365/201
• US Class Current: 714/723
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test configuration that includes a device and a method for testing the device in which test results determined during the testing of the device are stored in a memory in the device. In this way, the test results are connected with the device and available at any time for later evaluations.

Claims

1. A method for testing a semiconductor memory, which comprises:

providing the semiconductor memory with a nonvolatile memory and a multiplicity of individual memory cells;

using a test method to test the semiconductor memory and to determine test results, and for testing the individual memory cells with regard to a correct operation mode;

storing the test results in the nonvolatile memory in the semiconductor memory to make the test results available to the semiconductor memory throughout the service life of the semiconductor memory; and

storing an identifier in the nonvolatile memory to indicate the test method used to determine the test results.

2. The method according to claim 1, which comprises:

providing the nonvolatile memory as an electrically programmable nonvolatile memory.

3. The method according to claim 1, which comprises reading out and evaluating the stored test results.

4. The method according to claim 1, which comprises:

defining the test method as a first test method;

utilizing the test results from the first test method in a second test method;

rating a plurality of test results in a form of a quality class; and

storing the plurality of the test results.

5. The method according to claim 1, wherein the semiconductor memory is a DRAM.

6. A test configuration, comprising:

a test unit for performing testing according to a predetermined test method;

a programming unit; and

a semiconductor memory including;

a multiplicity of individual memory cells;

a nonvolatile memory; and

an input/output interface for performing an operation selected from the group consisting of writing data to said nonvolatile memory and reading data from said nonvolatile memory, said interface enabling connection of said test unit thereto such that said test unit can test said semiconductor memory according to the predetermined test method, for testing the individual memory cells with regard to a correct operation mode;

said interface also configured for connecting said programming unit thereto;

said programming unit configured for writing test results to said nonvolatile memory of said semiconductor memory, to store an identifier in said nonvolatile memory for indicating the test method used, thus making the test results available to the semiconductor memory throughout the service life of the semiconductor memory.

7. The test configuration according to claim 6, wherein said nonvolatile memory is an electrically programmable nonvolatile memory.

8. The test configuration according to claim 7, wherein said nonvolatile memory of said semiconductor memory stores data selected from the group consisting of the test results and a quality class determined during the testing of said semiconductor memory.

9. The test configuration according to claim 6, wherein said nonvolatile memory of said semiconductor memory stores data selected from the group consisting of the test results and a quality class determined during the testing of said semiconductor memory.

10. The test configuration according to claim 6, wherein said programming unit is integrated on said semiconductor memory.

11. The test configuration according to claim 6, wherein said semiconductor memory is a DRAM.

12. A method for testing a semiconductor memory, which comprises:

providing the semiconductor memory with a nonvolatile memory;

using a test method to test the semiconductor memory and to determine test results;

storing the test results in the nonvolatile memory in the semiconductor memory;

storing an identifier in the nonvolatile memory to indicate the test method used to determine the test results;

defining the test method as a first test method;

utilizing the test results from the first test method in a second test method;

rating a plurality of test results in a form of a quality class; and

storing the plurality of the test results.