System and method for adjusting group delay

• US 6,897,724 B2
• Filed: 03/19/2004
• Issued: 05/24/2005
• Est. Priority Date: 08/24/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Powerwave Technologies Incorporated
• Inventors: He, Jianqing, Gurvich, Mark, Rabinovich, Alex, Maslennikov, Nikolai
• Primary Examiner(s): Choe, Henry
• Application Number:
  US10/805,666
• Publication Number:
  US 20040178848A1
• Time in Patent Office: 431 Days
• Field of Search: 330/151, 330/149, 375/297, 455/63
• US Class Current: 330/151
• CPC Class Codes: H03F 1/3229 using a loop for error extraction and another loop for error subtraction

Abstract

A group delay adjusting circuit. The group delay adjusting circuit comprises an electronically adjustable variable capacitance, and an electronically variable virtual inductor coupled in parallel to the electronically variable capacitance at a node.

Claims

1. A feedforward amplifier comprising:

a main amplifier gain path including a first group delay adjuster having a virtual inductor; and

an error amplifier gain path including a second group delay adjuster having a virtual inductor having an output coupled to an output of the main amplifier gain path,

wherein each of the virtual inductors includes a quarter wavelength transmission line coupled to a variable shunt capacitor.

2. The feed forward amplifier of claim 1, in which the main amplifier gain path comprises the first group delay adjuster having a virtual inductor having an output coupled to an input of a first phase and gain adjuster and a first phase and gain adjuster output coupled to an input of a main amplifier.

3. The feed forward amplifier of claim 1, in which the error amplifier gain path comprises the second group delay adjuster having a virtual inductor having an output coupled to an input of a second phase and gain adjuster and a second phase and gain adjuster output coupled to an input of an error amplifier.