Programmable sliding window for image processing

• US 6,900,811 B2
• Filed: 01/17/2002
• Issued: 05/31/2005
• Est. Priority Date: 01/18/2001
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: LightSurf Technologies, Inc. (VeriSign, Inc.)
• Inventors: Sandford, Mark J.
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): NGUYEN, HAU H
• Application Number:
  US10/052,707
• Publication Number:
  US 20020135586A1
• Time in Patent Office: 1,230 Days
• Field of Search: 345/536, 345/538, 345/562, 345/539, 345/548, 345/654, 345/543, 345/806, 715/781, 715/806, 711/171
• US Class Current: 345/539
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 5/20 using local operators

Abstract

A sliding window (block) system incorporating a methodology for providing a processor access to image data is described. In an exemplary embodiment, the system operates as follows. An image is received for processing that has a size that is too large for the processor to access directly. As a result, the sliding window system creates first, second, and third swappable windows (blocks) for accessing image data from the image; each windows is swappable so that any two are available within the memory space of the processor while a third is being loaded in a background memory. The system cycles through the three windows such that, at any given point in time, two of the three windows are affixed in the memory space of the processor as left and right adjacent windows, while the remaining or third window is being loaded in the background (e.g., in a DRAM) as a temporary shadow or background window. After the shadow window is loaded with appropriate image data, it is brought into the foreground (i.e., within the memory space of the processor) as the new right window. The prior (old) right window now becomes the new left window; the prior (old) left window now becomes a new shadow or background window. The process repeats as necessary, until all image data of the target image has been accessed/processed.

Claims

1. An improved method for providing a processor access to image data, said processor having a memory space of a given size, the method comprising:

receiving an image for processing;

creating first, second, and third swappable windows for accessing image data from said image, said windows being swappable so that any two are available within the memory space of the processor while a third is being loaded in a background memory;

after initializing two of the windows with image data from said image and affixing those windows in the memory space of the processor as left and right adjacent windows, providing access to image data by performing substeps of;

i. loading the window that is not affixed in the memory space of the processor with image data from said image, said window temporarily comprising a shadow window that is loaded in the background memory,

ii. swapping said windows such that the left window is removed from the memory space of the processor, the right window now becomes the left window in the memory space of the processor, the shadow window now becomes the right window in the memory space of the processor, and the left window removed from the memory space of the processor now becomes a temporary shadow window to be loaded in the background memory, and

iii. providing access to the then-current left and right windows in the memory space of the processor for supporting image processing of said image.

2. The method of claim 1, repeating substeps i-iii until the entire image has been processed.

3. The method of claim 1, wherein said image comprises a megapixel image.

4. The method of claim 1, wherein said processor comprises a digital signal processor (DSP) having a small address space relative to the image.

5. The method of claim 1, wherein each said window comprises an 8×

8 pixel window.

6. The method of claim 1, wherein any two windows present in the address space of the processor are organized as a 16×

8 pixel block.

7. The method of claim 1, wherein the background memory comprises a DRAM.

8. The method of claim 1, wherein the background memory has an address space that is not directly accessible to the processor.

9. The method of claim 1, wherein the image has a size that is too large for the processor to access directly.

10. The method of claim 1, wherein the image has a size that is not too large for the processor to access directly.

11. The method of claim 1, wherein each of the values within each window is at a fixed memory address location relative to the window, as the window slides across the image.

12. The method of claim 1, wherein the image is processed by vertically sliding the windows across the image.

13. The method of claim 1, wherein the image is processed by horizontally sliding the windows across the image.

14. The method of claim 1, wherein the image is processed by both vertically and horizontally sliding the windows across the image.

15. The method of claim 1, wherein each said window comprises a pixel window having a bit width appropriate for a digital imaging processing application of interest.

16. The method of claim 15, wherein the digital imaging processing application of interest includes digital filtering of an image of a given size.

17. The method of claim 1, further comprising:

providing additional windows, so that the method may affix additional windows in the memory space of the processor at a given point in time.

18. The method of claim 1, further comprising:

providing additional windows, so that the method may background load additional windows in the memory space of the processor at a given point in time.

19. An apparatus for facilitating digital image processing, the apparatus comprising:

multiple two-dimensional image storage elements, including active and background ones, wherein the two-dimensional image storage elements comprise at least two active windows that are active in an address space of a processor and at least one shadow window that is not active in the address space of the processor;

a first control mechanism to temporarily map some of the two-dimensional image storage elements into the address space of the processor, whereupon those two-dimensional image storage elements become active in the address space of the processor;

a mechanism to background load one of the two-dimensional image storage elements that is not currently active in the address space of the processor; and

a second control mechanism to swap in the two-dimensional image storage element that has been background loaded into the address space of the processor, whereupon that two-dimensional image storage element becomes active in the address space of the processor.

20. The apparatus of claim 19, wherein, upon activation of said second control mechanism, one of the active two-dimensional image storage elements is no longer active in the address space of the processor.

21. The apparatus of claim 19, wherein said mechanism to background load includes a DMA engine.

22. The apparatus of claim 21, wherein said DMA engine issues an interrupt to signal the processor when background loading has completed.

23. The apparatus of claim 19, wherein said processor comprises a digital signal processor (DSP).

24. The apparatus of claim 19, wherein said at least two active windows comprise left and right active windows.

25. The apparatus of claim 19, wherein after a shadow window is loaded with appropriate image data and brought into the address space of the processor, the then-current right active window now becomes a new left active window, the prior left window now becomes a new shadow window, and the just-loaded shadow window now becomes a new right active window.

26. The apparatus of claim 19, wherein the digital image is processed by vertically sliding the windows across the digital image.