Method of making a semiconductor device having a low K dielectric

• US 6,903,004 B1
• Filed: 12/16/2003
• Issued: 06/07/2005
• Est. Priority Date: 12/16/2003
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Spencer, Gregory S., Turner, Michael D.
• Primary Examiner(s): THAI, LUAN C
• Application Number:
  US10/736,853
• Publication Number:
  US 20050130405A1
• Time in Patent Office: 539 Days
• Field of Search: 438622-629
• US Class Current: 438/624
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A low K dielectric layer and a cap for the low K dielectric layer are formed in situ using the same silicon precursors but at different precursor ratios. The low K dielectric is deposited with precursors that are useful for making a low K dielectric. Trenches are formed in the low K dielectric and are filled by a metal layer. Chemical mechanical processing (CMP) is utilized to remove the metal outside the trench while the cap aids planarity outside the trench.

Claims

1. A method comprising:

forming a dielectric overlying a substrate of a wafer, wherein the forming the dielectric further comprises;

forming a low K dielectric layer overlying the substrate by a chemical vapor deposition (CVD) process using a silicon precursor, wherein a dielectric constant of the low K dielectric layer is less than 3.0;

forming a second dielectric layer overlying the low K dielectric layer by a CVD process using the silicon precursor;

forming a void in the dielectric including in the low K dielectric layer and the second dielectric layer;

depositing a material over the wafer including depositing the material in the void;

removing portions of the material exterior to the void by polishing the wafer with a chemical mechanical polishing (CMP) process wherein the polishing removes at least some of the second dielectric layer.

2. The method of claim 1 wherein the silicon precursor includes a OctaMethylCycloTetraSiloxane(OMCTS) material.

3. The method of claim 1 wherein the silicon precursor includes a TetraMethylCycloTetraSiloxane(TMCTS) material.

4. The method of claim 1 wherein the silicon precursor includes molecules having a cyclic siloxane structure.

5. The method of claim 1 wherein the forming the low K dielectric layer and the forming the second dielectric layer includes maintaining continuous plasma using the silicon precursor.

6. The method of claim 5 wherein the maintaining the continuous plasma further includes providing plasma using the silicon precursor and oxygen at a first ratio of silicon precursor to oxygen during the forming the low K dielectric layer and providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen during the forming the second dielectric layer, wherein the first ratio is greater than the second ratio.

7. The method of claim 1 wherein:

the forming the low K dielectric layer includes providing plasma using the silicon precursor and oxygen at a first ratio of silicon precursor to oxygen;

wherein the forming the second dielectric layer includes providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen;

wherein the first ratio is greater than the second ratio.

8. The method of claim 7 wherein the first ratio is greater than or equal to 2 milligrams per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

9. The method of claim 7 wherein the second ratio is less than or equal to 1 milligram per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

10. The method of claim 1 wherein the low K dielectric layer has a dielectric constant of less than 2.8.

11. The method of claim 1 wherein the low K dielectric layer has a thickness of 2000 Angstroms or greater.

12. The method of claim 1 wherein the chemical vapor deposition (CVD) process used in forming the low K dielectric layer includes is performed with a deposition in a range of 4-10 Torr.

13. The method of claim 1 wherein no K value degrading processes are performed on the low K dielectric layer prior to the forming the second dielectric layer.

14. The method of claim 1 wherein the material is a conductive material.

15. The method of claim 1 wherein the low K dielectric layer is formed on a surface of the wafer including on conductive material and on another dielectric.

16. The method of claim 1 wherein the second layer has a hardness and the low K dielectric layer has a hardness, wherein the hardness of the second dielectric layer is greater than the hardness of the low K dielectric layer.

17. The method of claim 1 wherein a portion of the second dielectric layer remains after the removing portions of the material exterior to the void.

18. A method of making a dielectric comprising:

forming a low K dielectric layer overlying a wafer substrate by a chemical vapor deposition (CVD) that includes providing plasma using a silicon precursor and oxygen at a first ratio of silicon precursor to oxygen, the silicon precursor including at least one of a OctaMethylCycloTetraSiloxane(OMCTS) material and a TetraMethylCycloTetraSiloxane(TMCTS) material, wherein a dielectric constant of the low K dielectric layer is less than 3.0, and

forming a second dielectric layer on the low K dielectric layer by a CVD process that includes providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen;

wherein the first ratio is greater than the second ratio.

19. The method of claim 18 wherein the first ratio is greater than or equal to 2 milligrams per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

20. The method of claim 18 wherein the second ratio is less than or equal to 1 milligrams per minute of silicon precursor to 1 standard cubic centimeter of oxygen.

21. A semiconductor device comprising:

a substrate;

an interconnect overlying the substrate, the interconnect comprising;

a dielectric overlying the substrate, the dielectric including a low K dielectric layer and a second dielectric layer overlying the low K dielectric layer, the low K dielectric layer having a dielectric constant of less than 3.0, the second dielectric layer having a silicon to carbon intensity ratio of less than about 175 to 1 by time of flight secondary ion mass spectroscopy; and

a conductive interconnect structure located in a void of the dielectric, the void including a void in the low K dielectric layer and a void in the second dielectric layer;

wherein the second dielectric layer and the conductive interconnect structure each have a surface substantially coplanar with each other.

22. A method comprising:

forming a dielectric overlying a substrate of a wafer, wherein the forming the dielectric further comprises;

forming a low K dielectric layer overlying the substrate by a chemical vapor deposition (CVD) that includes providing plasma using a silicon precursor and oxygen at a first ratio of silicon precursor to oxygen, the silicon precursor including at least one of a OctaMethylCycloTetraSiloxane(OMCTS) material and a TetraMethylCycloTetraSiloxane(TMCTS) material;

forming a second dielectric layer overlying the low K dielectric layer by a CVD process that includes providing plasma using the silicon precursor and oxygen at a second ratio of silicon precursor to oxygen;

wherein the first ratio is greater than the second ratio;

forming a void in the dielectric including in the low K dielectric layer and the second dielectric layer;

depositing a material over the wafer including depositing the material in the void; and

removing portions of the material exterior to the void by polishing the wafer with a chemical mechanical polishing (CMP) process wherein the polishing removes at least some of the second dielectric layer.