Integrated circuit having integrated programmable gate array and field programmable gate array, and method of operating the same

• US 6,904,586 B1
• Filed: 03/25/2002
• Issued: 06/07/2005
• Est. Priority Date: 03/25/2002
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Entin, Bruce L., Bemanian, Majid, Scharf, William D.
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US10/105,579
• Time in Patent Office: 1,170 Days
• Field of Search: 716/16, 716/17, 716/8, 716/1, 326/39, 326/40, 326/41, 710/5, 710/305
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes at least two interfaces, a field-programmable gate array (FPGA) and a programmable gate array (PGA). The FPGA has a configuration memory associated therewith and is coupled to the at least two interfaces for communicating data therebetween. The PGA is coupled to and configured to cooperate with the FPGA to adapt the IC to a particular surrounding environment.

Claims

1. An integrated circuit (IC), comprising:

at least two interfaces;

a programmable gate array (PGA) coupled to said at least two interfaces for communicating data therebetween; and

a field-programmable gate array (FPGA) having a configuration memory associated therewith and coupled to and configured to cooperate with said PGA to adapt said IC to a particular surrounding environment, said PGA and FPGA integrated in said IC.

2. The IC as recited in claim 1 further comprising a standard input-output interface.

3. The IC as recited in claim 1 further comprising a second standard input-output interface.

4. The IC as recited in claim 1 further comprising a double data rate interface.

5. The IC as recited in claim 1 further comprising a co-processor coupled to embedded memory.

6. The IC as recited in claim 1 wherein said at least two interfaces are selected from the group consisting of:

a system physical interface (SPI), and

a 10-Gigabit Attachment Unit Interface (XAUI).

7. The IC as recited in claim 1 further comprising a bus expander coupled to said PGA.

8. A method of manufacturing an integrated circuit (IC) suited for a particular application, comprising:

forming an integrated circuit having a substrate, at least two interfaces, and including integrating in said integrated circuit a field-programmable gate array (FPGA) and a programmable gate array (PGA);

configuring said PGA with at least a portion of a design; and

subsequently providing a configuration program to configure said FPGA to cooperate with said PGA to adapt said IC to a particular surrounding environment.

9. The method as recited in claim 8 further comprising forming a standard input-output interface on said substrate.

10. The method as recited in claim 8 further comprising forming a second standard input-output interface on said substrate.

11. The method as recited in claim 8 further comprising forming a double data rate interface on said substrate.

12. The method as recited in claim 8 further comprising forming a co-processor on said substrate.

13. The method as recited in claim 8 wherein said at least two interfaces are selected from the group consisting of:

a system physical interface (SPI), and

a 10-Gigabit Attachment Unit Interface (XAUI).

14. The method as recited in claim 8 further comprising forming a bus expander on said substrate.