SOI device with reduced drain induced barrier lowering

• US 6,905,918 B2
• Filed: 12/29/2003
• Issued: 06/14/2005
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mouli, Chandra V.
• Primary Examiner(s): Blum, David S.
• Application Number:
  US10/747,586
• Publication Number:
  US 20040142520A1
• Time in Patent Office: 533 Days
• Field of Search: 438/149, 438/154, 438/217, 438/459, 257/262, 257/347
• US Class Current: 438/149
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Claims

1. A method for semiconductor processing, comprising:

providing a substrate having a semiconductor layer overlying an insulating layer;

doping desired regions of the insulating layer with electrical dopant, wherein a concentration of the dopant in the desired regions is at least about 10²⁰/cm³ after doping;

forming transistor devices in the semiconductor layer, the transistor devices each having a channel region and a gate region; and

diffusing dopant from the desired regions out into the channel regions of the transistor devices by exposing the substrate to an elevated temperature, wherein a concentration of dopant in the channel regions defines a retrograde dopant profile after diffusing.

2. The method of claim 1, wherein the concentration of the dopant in the channel regions is at least about 9×

10¹⁷/cm³.

3. The method of claim 1, wherein doping occurs between steps of forming transistor devices.

4. The method of claim 1, wherein doping comprises implanting n-type dopant into some desired regions and implanting p-type dopant into other desired regions.

5. The method of claim 4, wherein forming transistor devices comprises forming complementary transistor devices.

6. The method of claim 4, wherein the p-type dopant comprises phosphorus and the n-type dopant comprises boron.

7. The method of claim 6, wherein doping forms borophosphosilicate glass (BPSG) within the insulating layer.

8. The method of claim 1, further comprising implanting dopant into the gate regions of the transistor devices to adjust threshold voltages of the devices.

9. The method of claim 1, wherein forming transistor devices comprises forming a source positioned adjacent the channel region and forming a drain positioned adjacent the channel region and opposite the source.

10. The method of claim 9, wherein the source, the drain and the channel region are formed completely above the desired regions.

11. The method of claim 9, wherein the source and drain are doped complementarily to the channel region.

12. The method of claim 11, wherein forming transistor devices comprises forming at least one of an NMOS and a PMOS device.

13. The method of claim 12, wherein forming transistor devices comprises forming an NMOS device and a PMOS device, the NMOS and PMOS devices together comprising a CMOS device.

14. The method of claim 1, wherein exposing the substrate to an elevated temperature comprises forming a passivation layer.

15. The method of claim 1, wherein the substrate is a Separation by IMplanted OXygen (SIMOX) wafer.

16. The method of claim 1, wherein the semiconductor layer is an epitaxial silicon layer.

17. The method of claim 1, wherein the insulating layer comprises a buried silicon dioxide layer.

18. A method for forming transistor devices, comprising:

providing a semiconductor wafer having a silicon layer positioned above an insulating layer;

implanting electrical dopants substantially adjacent an interface between the insulating layer and the silicon layer to form dopant diffusion sources in the insulating layer; and

forming transistor devices in the silicon layer, the transistor devices each having channel and gate regions, wherein channel and gate regions of the transistor devices are formed completely above the dopant diffusion sources,

wherein retrograde doping profiles in the channel regions are established by diffusion of the dopants out of the diffusion sources and into the channel regions, wherein diffusion is caused by forming transistor devices.

19. The method of claim 18, wherein implanting electrical dopants forms dopant diffusion sources having a dopant concentration of at least about 10²⁰/cm³.

20. The method of claim 18, wherein forming transistor devices comprises forming a source positioned adjacent the gate region and the channel region and forming a drain positioned adjacent the gate and the channel region and opposite the source, wherein the source, the gate region, the channel region and the drain are all formed completely above the dopant diffusion sources.

21. The method of claim 18, further comprising implanting electrical dopants into the gate regions of the transistor devices to adjust threshold voltages of the devices.

22. The method of claim 19, further comprising doping the source and the drain complementarily to the channel region.

23. The method of claim 22, wherein forming transistor devices comprises implanting n-type and p-type dopants into the silicon layer to create n-wells and p-wells, respectively.

24. The method of claim 18, wherein the insulating layer comprises silicon dioxide.