Hardware support for partitioning a multiprocessor system to allow distinct operating systems

• US 6,910,108 B2
• Filed: 01/09/2002
• Issued: 06/21/2005
• Est. Priority Date: 01/09/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Downer, Wayne A., Gilbert, Bruce M., Lovett, Thomas D.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US10/045,923
• Publication Number:
  US 20030131067A1
• Time in Patent Office: 1,259 Days
• Field of Search: 711/141, 711/145, 711/173, 711/154, 711/201, 711/206, 711/214, 711/215, 709/201, 709/213, 707/8, 707/201
• US Class Current: 711/141
• CPC Class Codes: G06F 2209/541 Client-server
• CPC Class Codes: G06F 9/54 Interprogram communication

Abstract

A system and method of partitioning a multiprocessor or multinode computer system containing two or more partitions each of which contain at least three nodes or processors and a central hardware device communicating with a requestor node or processor, a target node or processor and at least one additional node or processor in the partition. The multiprocessor system architecture allows for partitioning resources to define separate subsystems capable of running different operating systems simultaneously. The method operates with the central device, a tag and address crossbar system, which transmits requests for data from the requestor node to the target node, but not to any of the additional nodes or processors which are not defined as part of a given partition. The method provides steps of assignment of definitions to physical ports with the central device corresponding with desired partitioning of resources within the system. Data processed within the system is assigned tags which themselves are related to the defined system resources allocated to one or more desired partitions within the system.

Claims

1. A multiprocessor computer system capable of being partitioned into one or more independently functioning processing systems comprising:

a plurality of processing nodes, each node including memory which is accessible locally by the node associated with said memory and remotely by any other node;

a shared, distributed system memory;

a communications pathway which interconnects said plurality of processing nodes, each node capable of operating independently, wherein each one of said processing nodes includes at least one processor and a portion of said shared system memory coupled to said processor and said communication pathway, and wherein said communication pathway is comprised of a central hardware device including tag and address means to communicate the identification of data transactions being processed through the system connected to said plurality of processing nodes, said tag and address means including means to store information related to the identification of a partition to which said data is associated, said central hardware device storing information for determining which nodes are storing copies of data which is associated with a given partition;

means to define one or more partitions to which one or more of said nodes are a member; and

means to associate each data transaction processed in the system to direct data only to such nodes defined as within the same partition of said data, including dispatch means which interconnect with said ports but allow communications with said ports only for data transactions defined for a partition for which said port is a member.

2. The multiprocessor system of claim 1, wherein said tag and address means further includes a register means associated with each node, said register means separably connected through said communications pathway only to one of said nodes, whereby each of said register means is connected to only one of said nodes, where each said register means accepts and forwards data transactions only identified as valid for the partition which said resister is connected.

3. The multiprocessor system of claim 2, wherein further said tag and address means includes dispatch means which restrict output of data transactions to only nodes which are defined within the partition with which the data is identified, and a second target node which is the destination of the requested data, wherein further said central hardware device transmits requests from the said requesting node to the said target node but not to any other node.

4. A multiprocessor computer system capable of being partitioned into one or more independently functioning processing systems comprising:

a plurality of processing nodes, each node capable of operating independently;

a shared, distributed system memory;

a communications pathway which interconnects said plurality of processing nodes, wherein each one of said processing nodes includes at least one processor and a portion of said shared system memory coupled to said processor and said communication pathway, wherein said communication pathway is comprised of a central hardware device including tag and address means to communicate the identification of data transactions being processed through the system connected to said plurality of processing nodes, said tag and address means including a first register means to store information related to the identification of a partition to which said data in associated, and a second register means to define at most one partition to which one or more of said nodes are a member; and

means to associate each data transaction processed in the system such as to direct data only to such nodes defined as within the same partition of said data,

wherein said tag and address means further includes a registers means associated with each node, said register means separately connected through said communications pathway only to one of said nodes, whereby each of said register means is connected to only one of said nodes, wherein each said register means accepts and forwards data transactions only identified as valid for the partition which said register is connected.

5. The multiprocessor system of claim 4, wherein further said tag and address means includes dispatch means which restrict output of data transactions to only nodes which are defined within the partition with which the data is identified, and a second target node which is the destination of the requested data, wherein further said central hardware device transmits requests from the said requesting node to the said target node but not to any other node.

6. A multiprocessor computer system capable of being partitioned into one or more independently functioning processing systems comprising:

a plurality of processing nodes, each node capable of operating independently;

a shared, distributed system memory;

a communications pathway which interconnects said plurality of processing nodes, wherein each one of said processing nodes includes at least one processor and a portion of said shared system memory coupled to said processor and said communication pathway, wherein said communication pathway is comprised of a central hardware device including tag and address means to communicate the identification of data transactions being processed through the system connected to said plurality of processing nodes, said tag and address means including first register means to store information related to the identification of a partition to which said data is associated, and a second register means to define at most one partition to which one or more of said nodes are a member; and

means to associate each data transaction processed in the system such as to direct data only to such nodes defined as within the same partition of said data,

wherein said tag and address means includes dispatch means which restrict output of data transactions to only nodes which are defined within the partition with which the data is identified, and a second target node which is the destination of the requested data, wherein further said central hardware device transmits requests from the said requesting node to the said target node but not to any other node.

7. The multiprocessor system of claim 6, wherein further said tag and address means includes dispatch means which restrict output of data transactions to only nodes which are defined within the partition with which the data is identified, and a second target node which is the destination of the requested data, wherein further said central hardware device transmits requests from the said requesting node to the said target node but not to any other node.

8. In a multiprocessor computer system comprising a plurality of processing nodes;

a shared, distributed system memory; and

a communication pathway connecting said processing nodes;

wherein each one of said processing nodes includes at least one processor; and

a portion of said shared system memory coupled to said processor and said communication pathway;

each node including memory which is accessible locally by the node associated with said memory and remotely by any other node;

said communications pathway comprised of communications ports each dedicated to communicating with one of said processing nodes;

a method for partitioning the resources of the system into two or more partitions;

the method comprising the steps of;

assigning a physical address to at least two of said ports;

assigning a logical address to each said physical address;

storing said logical address in a memory;

defining each of said processing nodes to correspond to no more than one partition, such that said ports are interconnected with a dispatch mechanism that allows communications with said ports only for data transactions defined for a partition for which said port is a member, and;

routing data within the system to correspond with the addresses of the resources defined as a partition, via a central hardware device of said communication pathway storing information for determining which nodes are storing copies of data which is associated with a given partition.

9. The method of claim 8 wherein one or more of said processing nodes may be defined as corresponding to no partition.

10. The method of claim 8 farther including the step of labeling data requests within the system to a logical address corresponding to the partition issuing said request.

11. In a multiprocessor computer system comprising a plurality of processing nodes;

a shared, distributed system memory; and

a communication pathway connecting said processing nodes;

wherein each one of said processing nodes includes at least one processor; and

a portion of said shared system memory coupled to said processor and said communication pathway;

each node including memory which is accessible locally by the node associated with said memory and remotely by any other node;

said communications pathway comprised of communications ports each dedicated to communicating with one of said processing nodes;

a method for partitioning the resources of the system into two or more partitions;

the method comprising the steps of;

assigning a physical address to each of said ports;

assigning a logical address to each said physical address;

storing said logical address in a memory;

defining each logical address to correspond to no more than one partition, such that said ports are interconnected with a dispatch mechanism that allows communications with said ports only for data transactions defined for a partition for which said port is a member;

assigning identification to each data transaction within the system which corresponds to the logical address to which the transaction is associated;

comparing said identified transaction with said logical address in memory corresponding to only one partition; and

routing data within the system to said ports defined as a member of the partition with which the data is associated, via a central hardware device of said communication pathway storing information for determining which nodes are storing copies of data which is associated with a given partition.

12. The method of claim 11 further including the step of routing data requests within the system to a cache memory within said communications pathway with a logical address corresponding to the partition issuing said request, with said cache memory physically interconnected only with a port assigned to a physical address.

13. A multiprocessor computer system capable of being partitioned into one or more independently functioning processing systems comprising:

a plurality of processing nodes, each node capable of operating independently;

a shared, distributed system memory;

a communications pathway which interconnects said plurality of processing nodes, wherein each one of said processing nodes includes at least one processor and a portion of said shared system memory coupled to said processor and said communication pathway, wherein said communication pathway is comprised of a central hardware device including a tag and address mechanism to communicate the identification of data transactions being processed through the system connected to said plurality of processing nodes, said tag and address mechanism including a first register to store information related to the identification of a partition to which said data is associated, and a second register to define at most one partition to which one or more of said nodes are a member; and

a mechanism to associate each data transaction processed in the system such as to direct data only to such nodes defined as within the same partition of said data,

wherein said tag and address mechanism further includes a registers associated with each node, said register separately connected through said communications pathway only to one of said nodes, whereby each of said register is connected to only one of said nodes, wherein each said register accepts and forwards data transactions only identified as valid for the partition which said register is connected.

14. A multiprocessor computer system capable of being partitioned into one or more independently functioning processing systems comprising:

a plurality of processing nodes, each node capable of operating independently;

a shared, distributed system memory;

a communications pathway which interconnects said plurality of processing nodes, wherein each one of said processing nodes includes at least one processor and a portion of said shared system memory coupled to said processor and said communication pathway, wherein said communication pathway is comprised of a central hardware device including a tag and address mechanism to communicate the identification of data transactions being processed through the system connected to said plurality of processing nodes, said tag and address mechanism including a first register to store information related to the identification of a partition to which said data is associated, and a second register to define at most one partition to which one or mare of said nodes are a member; and

a mechanism to associate each data transaction processed in the system such as to direct data only to such nodes defined as within the same partition of said data,

wherein further said tag and address mechanism includes a dispatch mechanism which restrict output of data transactions to only nodes which are defined within the partition with which the data is identified, and a second target node which is the destination of the requested data, wherein further said central hardware device transmits requests from the said requesting node to the said target node but not to any other node.