Shared peripheral architecture

• US 6,915,367 B2
• Filed: 10/30/2003
• Issued: 07/05/2005
• Est. Priority Date: 09/13/2000
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Tyger, Karen, Gary, Sonya
• Primary Examiner(s): Rinehart, Mark H.
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US10/697,777
• Publication Number:
  US 20040088459A1
• Time in Patent Office: 614 Days
• Field of Search: 710240-244, 710113-118, 710/51, 710/309, 710/316, 710/317
• US Class Current: 710/244
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

Claims

1. An embedded computing system, comprising:

a plurality of processors;

a bus coupling to a plurality of peripheral units;

a multiplexor for coupling each of the plurality of processors to the bus in response to an owner signal; and

a set of peripheral-share registers wherein each member of the set resides at and is associated with a particular one of the plurality of peripheral units and includes an entry holding a state value indicating which of the plurality of processors currently owns the peripheral unit, wherein the owner signal is based on one of the state values such that only the one of the processors indicated as currently owning the peripheral is coupled by the multiplexor to the peripheral.

2. The system of claim 1, wherein the multiplexer is bi-directional and comprises:

an address multiplexor coupled to address outputs of each of the plurality of processors wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output based on the state of the owner signal;

a data multiplexor coupled to data outputs of each of the plurality of processors, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output based on the state of the owner signal; and

a shared register having an address port coupled to the MUX address output, a data port coupled to the MUX data output, and a bus port coupled to communicate with the bus.

3. The controller of claim 1, wherein one of the processors is dedicated to executing operating system code and another one of the processors is executing application code.

4. The controller of claim 1 wherein the set of peripheral share registers includes a plurality of request registers such that each request register corresponds to one of the plurality of processors, wherein each request register has an entry associated with each of the peripheral units, and wherein, each entry holds a value indicating whether the corresponding processor is requesting ownership of the associated peripheral unit.

5. The controller of claim 1 wherein the set of peripheral share registers includes a plurality of release registers such that each release register corresponds to one of the plurality of processors, wherein each release register has an entry associated with each of the peripheral units, and wherein, each entry holds a value indicating whether the corresponding processor is releasing ownership of the associated peripheral unit.

6. The controller of claim 1 wherein the set of peripheral share registers includes a priority register having an entry associated with each of the peripheral units, wherein each entry holds a value indicating which of the plurality of processors wins ownership of the associated peripheral unit when a conflict occurs between two or more of the processors requesting ownership of the associated peripheral unit.

7. The controller of claim 1, wherein the system further comprises the peripheral units and wherein the processors and the peripheral units comprise a single integrated circuit.

8. The controller of claim 1 wherein the state value is dynamically configurable during operation by at least one of the plurality of processors.

9. A multiprocessor controller, comprising:

first and second processor cores;

a plurality of peripherals;

a bus coupling the processor cores to the peripherals; and

means for arbitrating between the processor cores for communication access to requested ones of the peripherals, whereby each of the peripherals is only used by one of the core processors at a particular time, wherein the arbitrating means comprises logic for determining which of the processor cores is an owner of a requested one of the peripherals, wherein the arbitrating means further comprises a multiplexor for selectably coupling the processor cores to the bus in response to an owner signal, the multiplexor comprising;

an address multiplexor coupled to address outputs of the processor cores wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output based on a state of the owner signal; and

a data multiplexor coupled to data outputs of the processor cores, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output based on the state of the owner signal; and

a set of peripheral-share registers wherein each member of the set resides at and is associated with one of the plurality of peripherals and includes an entry that holds a state value indicating which of the processor cores currently owns the associated peripheral.

10. The controller of claim 9, wherein the bus comprises an address bus and a data bus for each of the processor cores.

11. The controller of claim 10, wherein the arbitrating means further comprises a multiplexor for selecting the address and data busses corresponding to one of the core processors to the bus in response to an owner signal corresponding to the ownership determination.

12. The controller of claim 9, wherein the arbitrating means further comprises a control register for each of the peripherals storing an ownership state indicating which of the core processors controls ownership.

13. The controller of claim 9, wherein the processor cores comprise embedded processor cores integrated on a single integrated circuit chip.

14. The controller of claim 13, further comprising:

a peripheral control register associated with each of the peripheral units, wherein the peripheral control register is shared amongst the plurality of processors and is integrated on the single integrated circuit chip.

15. A multiprocessor computing system, comprising:

a pair of processors;

a plurality of peripheral units;

a bus coupling to each of the peripheral units;

a multiplexor selectively coupling each of the processors to the bus, wherein the processors, the peripheral units, and the multiplexor comprise a single integrated circuit,

in the integrated circuit, a peripheral register associated with each of the peripheral units including en entry associated with each of the processors holding a state value indicating which one of the processors owns the associated peripheral unit, wherein the multiplexor performs the coupling based on the state values in the peripheral registers.

16. The system of claim 15, wherein the state value is dynamically configurable during operation by at least one of the processors.

17. The system of claim 15, wherein the multiplexor is bi-directional and comprises:

an address multiplexor coupled to address outputs of each of the processors wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output based on the state of the owner signal;

a data multiplexor coupled to data outputs of each of the processors, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output based on the state of the owner signal; and

a shared register having an address port coupled to the MUX address output, data port coupled to the MUX data output, and a bus port coupled to communicate with the bus.

18. The system of claim 17, wherein the set of peripheral share registers includes a plurality of request registers such that each request register corresponds to one of the processors, wherein each request register has an entry associated with each of the peripheral units, and wherein each entry holds a value indicating whether the corresponding processor is requesting ownership of the associated peripheral unit.

19. The system of claim 15, wherein one of the processors is dedicated to executing operating system code and another one of the processors is executing application code.