Semiconductor integrated circuit device with I/O cell and connection member

• US 6,919,632 B2
• Filed: 09/26/2002
• Issued: 07/19/2005
• Est. Priority Date: 09/27/2001
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sei, Toshikazu
• Primary Examiner(s): Pham, Hoai
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US10/254,659
• Publication Number:
  US 20030057549A1
• Time in Patent Office: 1,027 Days
• Field of Search: 257/280, 257723-725, 257/691
• US Class Current: 257/723
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate

Abstract

A semiconductor integrated circuit device includes connection members arranged on an entire chip, a first I/O cell which is arranged on the periphery of the chip and has a first end portion on the peripheral side of the chip and a second end portion on the center side of the chip, a second I/O cell which is arranged inside the first I/O cell and has a third end portion on the peripheral side of the chip and a fourth end portion on the center side of the chip, first terminals formed on the first end portion and connected to the connection members, second terminals formed on the second end portion and connected to an internal circuit of the chip, third terminals formed on the third end portion and connected to the internal circuit, and fourth terminals formed on the fourth end portion and connected to the connection members.

Claims

1. A semiconductor integrated circuit device comprising:

a chip;

connection members arranged on said entire chip and connected to an external circuit of said chip;

a first I/O cell which is arranged on a periphery of said chip and has a first end portion on a peripheral side of said chip and a second end portion on a center side of said chip;

a second I/O cell which is arranged inside said first I/O cell and has a third end portion on the peripheral side of said chip and a fourth end portion on the center side of said chip;

first terminals formed on the first end portion and connected to said connection members;

second terminals formed on the second end portion and connected to and internal circuit of said chip;

third terminals formed on the third end portion and connected to the internal circuit of said chip, both the second and third terminals disposed along a direction extending from the first end portion to the second end portion and opposed to each other;

fourth terminals formed on the fourth end portion and connected to said connection members;

a first ESD protective element provided in the first I/O cell and connected to the first terminal; and

a second ESD protective element provided in the second I/O cell and connected to the fourth terminal.

2. The disk apparatus according to claim 1, wherein

said first I/O cell comprises a plurality of first I/O cells which are arranged to be adjacent to each other on each side of said chip, and

said second I/O cell comprises a plurality of second I/O cells which are arranged to be adjacent to each other on each side of said chip.

3. A device according to claim 2, wherein

said plurality of second I/O cells are arranged with a partial gap.

4. A device according to claim 3,

at least one of a power supply interconnection which connects said first and second I/O cells to a power supply, and a ground interconnection which connects said first and second I/O cells to ground runs from a center of said chip to the gap in said second I/O cells.

5. A device according to claim 1, wherein

said second terminals face said third terminals.

6. A device according to claim 1, wherein

said connection members are staggered or arranged in a matrix on an entire surface of said chip.

7. A device according to claim 1, wherein

said first terminals are arranged on a center of said first I/O cell.

8. A device according to claim 1, wherein

said fourth terminals are arranged on a center of said second I/O cell.

9. A device according to claim 1, further comprising:

a third I/O cell which is arranged inside said second I/O cell and has a fifth end portion on the peripheral side of said chip and a sixth end portion on the center side of said chip;

a fourth I/O cell which is arranged inside said third I/O cell and has a seventh end portion on the peripheral side of said chip and an eighth end portion on the center side of said chip;

fifth terminals formed on the fifth end portion and connected to said connection members;

sixth terminals formed on the sixth end portion and connected to the internal circuit of said chip;

seventh terminals formed on the seventh end portion and connected to the internal circuit of said chip; and

eighth terminals formed on the eighth end portion and connected to said connection members.

10. A device according to claim 9, wherein

said first I/O cell comprises a plurality of first I/O cells which are arranged to be adjacent to each other on each side of said chip,

said second I/O cell comprises a plurality of second I/O cells which are arranged to be adjacent to each other on one side of said chip,

said third I/O cell comprises a plurality of third I/O cells which are arranged to be adjacent to each other in said one side of said chip, and

said fourth I/O cell comprises a plurality of fourth I/O cells which are arranged to be adjacent to each other in said one side of said chip.

11. A device according to claim 10, wherein

each of said second to fourth I/O cells are arranged with a partial gap.

12. A device according to claim 9, wherein

said sixth terminals face said seventh terminals.

13. A device according to claim 9, wherein

said second I/O cell is spaced apart from said third I/O cell by a predetermined distance, and

said connection members located between said second and third I/O cells are respectively connected to a power supply interconnection and a ground interconnection.

14. A device according to claim 13, wherein

said power supply interconnection and said ground interconnection run from said connection members located between said second and third I/O cells to a gap in said second I/O cell, and run to a gap of said third and fourth I/O cells.

15. A device according to claim 13, wherein

a region between said second and third I/O cells includes a region in which the internal circuit of said chip is present.

16. A device according to claim 1, wherein

a macrocell is arranged to be adjacent to said first or second I/O cell.

17. A device according to claim 16, wherein

said macrocell has ninth terminals and 10^th terminals,

the ninth terminals are formed on an end portion on the center side of said chip and connected to the internal circuit of said chip, and

the 10th terminals are formed on an end portion on the peripheral side of said chip and connected to said connection members.