Memory cell and method for forming the same

• US 6,921,935 B2
• Filed: 05/26/2004
• Issued: 07/26/2005
• Est. Priority Date: 06/21/2002
• Status: Expired due to Term

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Brown, Kris K.
• Primary Examiner(s): Dang, Phuc T.
• Application Number:
  US10/855,705
• Publication Number:
  US 20040219742A1
• Time in Patent Office: 426 Days
• Field of Search: 257/300, 257/302, 257/327, 257/329, 257/330, 257/334, 257/343, 257/378, 257/407, 257/412, 257/389
• US Class Current: 257/300
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Claims

1. A memory cell formed on a substrate having a surface, comprising:

an active region formed in the substrate;

a vertical transistor at least partially formed in an epitaxial post, the epitaxial post formed on the surface of the substrate and extending therefrom, the vertical transistor further having a gate formed around a perimeter of the epitaxial post; and

a capacitor formed on the vertical transistor.

2. The memory cell of claim 1, wherein the vertical transistor comprises:

a gate oxide formed on a surface defining the perimeter of the epitaxial post,the gate being formed on the gate oxide; and

insulating sidewalls formed on the gate.

3. The memory cell of claim 1, wherein the gate comprises polysilicon.

4. The memory cell of claim 1, wherein the capacitor comprises a container shaped capacitor structure.

5. The memory cell of claim 1, further comprising a diffusion region in the epitaxial post adjacent the capacitor.

6. The memory cell of claim 1, wherein the active region comprises a buried digit line.

7. The memory cell of claim 1, further comprising a digit line contact formed over the active region and proximate the vertical transistor.

8. The memory cell of claim 1, further comprising an insulating region formed around the perimeter of the epitaxial post and interposed between the capacitor and the vertical transistor.

9. The memory cell of claim 1, wherein the epitaxial post comprises a channel region.

10. A memory cell formed on a substrate having a surface, comprising:

a vertical transistor comprising;

an active region formed in the substrate;

an epitaxial post extending from the surface of the substrate; and

a gate formed to substantially extend around a perimeter of the epitaxial post; and

a capacitor formed on the vertical transistor.

11. The memory cell of claim 10, wherein the vertical transistor comprises:

a gate oxide formed on a surface defining the perimeter of the epitaxial post,the gate being formed on the gate oxide; and

insulating sidewalls formed on the gate.

12. The memory cell of claim 10, wherein the gate comprises polysilicon.

13. The memory cell of claim 10, wherein the capacitor comprises a container shaped capacitor structure.

14. The memory cell of claim 10, further comprising a diffusion region in the epitaxial post adjacent the capacitor.

15. The memory cell of claim 10, wherein the active region comprises a buried digit line.

16. The memory cell of claim 10, further comprising a digit line contact formed over the active region and proximate the vertical transistor.

17. The memory cell of claim 10, further comprising an insulating region formed around the perimeter of the epitaxial post and interposed between the capacitor and the vertical transistor.

18. The memory cell of claim 10, wherein the epitaxial post comprises a channel region.

19. A memory cell comprising:

a vertical transistor comprising;

a first source/drain region formed in the substrate;

a post extending from a surface of the substrate, the post having a second source/drain region formed therein; and

a gate formed from a semiconductor material, the gate formed at least partially around a perimeter of the post; and

a capacitor formed on the post.

20. The memory cell of claim 19, wherein the post comprises an epitaxial post.

21. The memory cell of claim 19, wherein the post comprises a channel region.

22. The memory cell of claim 19, wherein the gate extends peripherally about the epitaxial post.

23. A memory cell formed on a substrate having a surface, comprising:

an active region formed in the substrate;

a vertical transistor at least partially formed in an epitaxial post formed on the surface of the substrate over the active region, the vertical transistor having a gate formed at least partially around a perimeter of the epitaxial post; and

a capacitor formed on the epitaxial post.

24. The memory cell of claim 23, wherein the vertical transistor comprises:

a gate oxide formed on a surface defining the perimeter of the epitaxial post, the gate being formed on the gate oxide; and

insulating sidewalls formed on the gate.

25. The memory cell of claim 24, wherein the gate comprises polysilicon.

26. The memory cell of claim 23, wherein the capacitor comprises a container shaped capacitor structure.

27. The memory cell of claim 23, further comprising a diffusion region in the epitaxial post adjacent the capacitor.

28. The memory cell of claim 23, wherein the active region comprises a buried digit line.

29. The memory cell of claim 23, further comprising a digit line contact formed over the active region and proximate the vertical transistor.

30. The memory cell of claim 23, further comprising an insulating region formed around the perimeter of the epitaxial post and interposed between the capacitor and the vertical transistor.

31. The memory cell of claim 23, wherein the epitaxial post comprises a channel region.