CMOS image sensor system with self-reset digital pixel architecture for improving SNR and dynamic range

• US 6,927,796 B2
• Filed: 09/24/2001
• Issued: 08/09/2005
• Est. Priority Date: 09/24/2001
• Status: Active Grant

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Lim, Suk Hwan, Liu, Xinqiao, Gamal, Abbas El
• Primary Examiner(s): Ho, Tuan
• Assistant Examiner(s): JELINEK, BRIAN J
• Application Number:
  US09/962,804
• Publication Number:
  US 20030058360A1
• Time in Patent Office: 1,415 Days
• Field of Search: 348/308, 348/297, 348/294, 348/241, 348/248, 348/572, 250/208.1
• US Class Current: 348/297
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

A CMOS DPS image sensor architecture for improving SNR and dynamic range is presented. The CMOS DPS architecture includes self-reset digital pixels capable of collecting more charge than the physical well capacity. A method for improving SNR without reducing dynamic range in a CMOS video sensor system under low illumination is described, wherein the CMOS video sensor system employing self-reset DPS architecture includes pixel level A/D conversion and wherein each DPS pixels is capable of resetting itself whenever a corresponding diode reaches saturation during integration time.

Claims

1. A self-reset digital pixel sensor (DPS), comprising:

a diode capable of collecting more charge than physical well capacity of said DPS;

a feedback circuit capable of effecting at least one self-reset during a single integration whenever said diode reaches saturation;

a digitizing means capable of providing pixel level analog-to-digital conversion (ADC) converting analog pixel signal to digital pixel value;

a memory means coupled to said digitizing means for storing said digital pixel value; and

a comparing means coupled to said feedback circuit, said digitizing means, and said memory means for facilitating said at least one self-reset and said pixel level ADC.

2. The DPS of claim 1, wherein said diode is capable of collecting a total charge of m times said physical well capacity Q_well, wherein m is number of self-reset during said integration determined by a counting means.

3. The DPS of claim 1, wherein said DPS capable of capturing multiple pixel samples during said integration and said digitizing means capable of providing multiple ADC.

4. The DPS of claim 3, wherein peak signal-to-noise ratio (SNR) of said DPS is not limited by said physical well capacity.

5. The DPS of claim 4, wherein said peak SNR is increased approximately m times said physical well capacity, wherein m is number of self-reset during said integration determined by a counting means.

6. The DPS of claim 3, further comprising means for providing photocurrent estimation to reduce read noise whereby dynamic range of said DPS is extended at both high and low illumination ends.

7. The DPS of claim 1, further comprising means for providing mean-square-error estimation to reduce noise whereby dynamic range of said DPS is extended at both high and low illumination ends.

8. The DPS of claim 1, wherein peak signal-to-noise ratio (SNR) of said DPS is not limited by said physical well capacity.

9. The DPS of claim 8, wherein said peak SNR is increased m times said physical well capacity, wherein m is number of self-reset during said integration determined by a counting means.

10. A self-reset digital pixel sensor (DPS) architecture with self-reset DPS for improving signal-to-noise ratio (SNR) and extending dynamic range, wherein said DPS architecture capable of capturing multiple pixel samples during a single integration, said architecture comprising:

a diode capable of collecting more charge than physical well capacity of said DPS;

a feedback circuit capable of effecting at least one self-reset during said integration whenever said diode reaches saturation;

a digitizing means capable of providing multiple pixel level analog-to-digital conversions (ADCs) for converting analog pixel signals to corresponding digital pixel values during said integration;

a memory means coupled to said digitizing means for storing said digital pixel values; and

a comparing means coupled to said feedback circuit, said digitizing means, and said memory means for facilitating said at least one self-reset and said ADCs.

11. The DPS architecture of claim 10, wherein said diode is capable of collecting a total charge of m times said physical well capacity Q_well, wherein m is number of self-reset during said integration determined by a counting means.

12. The DPS architecture of claim 10, wherein peak SNR of said DPS is not limited by said physical well capacity.

13. The DPS architecture of claim 12, wherein said peak SNR is increased approximately m times said physical well capacity, wherein m is number of self-reset during said integration determined by a counting means.

14. The DPS architecture of claim 10, further comprising means for providing linear mean-square-error estimation to reduce read noise whereby dynamic range of said DPS is extended at low illumination end.

15. A complementary metal oxide semiconductor (CMOS) image sensor system with self-reset digital pixel sensor (DPS) architecture for improving signal-to-noise ratio (SNR) and extending dynamic range, wherein said DPS architecture capable of capturing multiple pixel samples during a single integration, said CMOS image sensor system comprising:

at least one self-reset DPS pixel, said DPS pixel comprising;

a diode capable of collecting more charge than physical well capacity of said DPS;

a feedback circuit capable of providing at least one self-reset during said integration whenever said diode reaches saturation;

a digitizing means capable of providing multiple pixel level analog-to-digital conversions (ADCs) for converting analog pixel signals to corresponding digital pixel values during said integration;

a memory means coupled to said digitizing means for storing said digital pixel values; and

a comparing means coupled to said feedback circuit, said digitizing means, and said memory means for facilitating said at least one self-reset and said ADCs; and

a counting means for determining number of self-reset occurred during said integration by analyzing number of pixel samples captured during said integration.

16. The CMOS image sensor system of claim 15, wherein said diode is capable of collecting a total charge of m times said physical well capacity Q_well, wherein m is said number of self-reset.

19. The CMOS image sensor system of claim 15, further comprising means for providing mean-square-error estimation to reduce noise whereby dynamic range of said DPS is extended at low illumination end.

17. The CMOS image sensor system 15, wherein peak SNR of said DPS is not limited by said physical well capacity.

18. The CMOS image sensor system of claim 17, wherein said peak SNR is increased approximately m times said physical well capacity, wherein m is said number of self-reset.

20. A method for simultaneously improving dynamic range and signal-to-noise (SNR) in a complementary metal oxide semiconductor (CMOS) image sensing system employing self-reset digital pixel sensor (DPS) architecture, wherein said self-reset DPS capable of resetting itself whenever said DPS reaches saturation during a single integration and wherein said self-reset DPS capable of collecting more charge than physical well capacity of said DPS, the method comprising the steps of:

capturing multiple pixel samples during said integration;

converting at pixel level captured analog pixel sample signals to corresponding digital pixel values;

storing said digital pixel values in memory;

obtaining at high speed said digital pixel values from said memory;

determining number of self-reset occurred during said integration by analyzing said digital pixel values;

determining total charge collected during said integration by analyzing said number of self-reset;

performing linear mean-square-error estimation to reduce noise associated with said capturing step thereby extending said dynamic range at low illumination end and increasing said SNR.