Integrated chemical microreactor, thermally insulated from detection electrodes, and manufacturing and operating methods therefor

• US 6,929,968 B2
• Filed: 06/23/2004
• Issued: 08/16/2005
• Est. Priority Date: 09/27/2000
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Villa, Flavio, Barlocchi, Gabriele
• Primary Examiner(s): Thompson, Craig A.
• Assistant Examiner(s): Harrison, Monica D.
• Application Number:
  US10/874,905
• Publication Number:
  US 20040226908A1
• Time in Patent Office: 419 Days
• Field of Search: 438/701, 438/700, 438/689, 438/580, 438/459, 438/197, 438/50, 438/48, 438/24, 435/287.2, 435/287.1, 435/283.1, 737/54
• US Class Current: 438/48
• CPC Class Codes: B01L 2200/12 Specific details about manufacturing devices
• CPC Class Codes: B01L 2300/0645 Electrodes
• CPC Class Codes: B01L 2300/0825 Test strips
• CPC Class Codes: B01L 2300/1827 using resistive heater
• CPC Class Codes: B01L 2300/1883 using thermal insulation
• CPC Class Codes: B01L 3/502707 characterised by the manufacture of the container or its components by shaping or joining plastic parts B29C59/00, B29C65/00; by laminating B32B37/00; manufacture of microstructural devices in general B81C
• CPC Class Codes: B01L 7/52 with provision for submitting samples to a predetermined sequence of different temperatures, e.g. for treating nucleic acid samples amplification or hybridisation processes per se C12Q1/68; controlling sequential reactions for synthesis B01J19/0046

Abstract

Integrated microreactor, formed in a monolithic body and including a semiconductor material region and an insulating layer; a buried channel extending in the semiconductor material region; a first and a second access trench extending in the semiconductor material region and in the insulating layer, and in communication with the buried channel; a first and a second reservoir formed on top of the insulating layer and in communication with the first and the second access trench; a suspended diaphragm formed by the insulating layer, laterally to the buried channel; and a detection electrode, supported by the suspended diaphragm, above the insulating layer, and inside the second reservoir.

Claims

1. A method for manufacturing a microreactor, comprising:

forming a monolithic body, said step of forming a monolithic body including forming a semiconductor material region;

forming a buried channel in said semiconductor material region;

forming a first and a second access cavity, said first and a second access cavity extending in said monolithic body as far as said buried channel;

forming a suspended diaphragm laterally to, but not over, said buried channel; and

forming a detection electrode on top of said suspended diaphragm.

2. A method according to claim 1, wherein said step of forming a monolithic body comprises the step of forming an insulating region on top of said region of semiconductor material, before said step of forming a detection electrode.

3. A method according to claim 2, further comprising the step of forming a heating electrode in said insulating region, over said buried channel.

4. A method according to claim 2, wherein said step of forming said suspended diaphragm comprises the step of selectively removing part of said semiconductor material region from the back, as far as said insulating region.

5. A method according to claim 1, wherein said step of forming a semiconductor material region comprises the steps of forming a monocrystalline substrate;

forming said buried channel in said monocrystalline substrate; and

growing an epitaxial layer on top of said monociystalline substrate and said buried channel.

6. A method according to claim 4, wherein said step of removing comprises etching said semiconductor material region using TMAH.

7. A method according to claim 5, wherein said step of forming a monocrystalline substrate comprises growing semiconductor material with <

110>

orientation, and in that said step of forming a buried channel comprises etching said monociystalline substrate along a parallel direction to an <

111>

orientation plane.

8. A method according to claim 7, wherein, during said step of etching said monocrystalline substrate, a grid-shaped mask is used with polygonal apertures, with sides extending at approximately 45°

with respect to said <

111>

orientation plane.

9. A method according to claim 7, wherein said monocrystalline substrate is etched using TMAH.

10. A method according to claim 5, wherein said step of forming a buried channel comprises masking said substrate through a grid-like hard mask, and etching said substrate through the hard mask.

11. A method according to claim 10, wherein said hard mask comprises a polycrystalline region, surrounded by a covering layer of dielectric material and said covering layer is removed after said etching step, and said epitaxial layer is grown on said polycrystalline region, thereby forming a polycrystalline layer, and on said substrate, thereby forming a monocrystalline region.

12. A method according to claim 10, wherein said hard mask comprises a dielectric material grid, and said epitaxial layer grows on said substrate and on said dielectric material grid, forming a monocrystalline region on said substrate, and a polycrystalline region on said dielectric material grid.

13. A method according to claim 12, wherein said first access cavity is substantially aligned with a first longitudinal end of said buried channel and said second access cavity is substantially aligned with a second longitudinal end of the buried channel.