Active SOI structure with a body contact through an insulator

• US 6,930,357 B2
• Filed: 06/16/2003
• Issued: 08/16/2005
• Est. Priority Date: 06/16/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Kang, Woo-Tag
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Thanh V.
• Application Number:
  US10/463,023
• Publication Number:
  US 20040253773A1
• Time in Patent Office: 792 Days
• Field of Search: 257/347, 257/349, 257/351, 257/301
• US Class Current: 257/347
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A silicon on insulator shaped structure formed to reduce floating body effect comprises a T-shaped active structure and a body contact for back bias. Etching a T-shape through two layers of oxide will form the T-shaped active areas. A back bias is formed when a metal line is dropped through the SOI structure and reaches a contact plug. This contact plug is doped with N+ or P+ dopant and is embedded in a Si substrate. The T-active shaped structure is used to reduce the short channel effects and junction capacitance that normally hinder the effectiveness of bulk transistors. The back bias is used as a conduit for generated holes to leave the SOI transistor area thus greatly reducing the floating effects generally associated with SOI structures.

Claims

1. A transistor in an integrated circuit having a silicon on insulator active structure, comprising:

a silicon substrate;

an insulator overlying the silicon substrate;

an epitaxially gown silicon layer extending through a first interruption in the insulator and physically touching the silicon substrate;

a gate overlying the epitaxially grown silicon layer;

a source disposed within the epitaxially grown silicon layer;

a drain disposed within the epitaxially grown silicon layer and in electrical communication with the source via a channel, the channel disposed within the epitaxially grown silicon layer and underlying the gate, wherein the first interruption is located adjacent the channel such that excess charge can be conducted away from the channel to the silicon substrate;

a body contact, in electrical communication with the first interruption in the insulator, for conducting the excess charge distally from the channel;

a second interruption in the insulator through which the excess charge escapes; and

silicon which resides in the second interruption.

2. The silicon on insulator shaped structure according to claim 1 further comprising a metal line that overlies the gate and is electrically coupled to the body contact.

3. The silicon on insulator shaped structure according to claim 1 wherein the silicon on insulator structure comprises a T-shape.

4. The silicon on insulator shaped structure according to claim 1, further comprising a metal line coupled to the body contact through the silicon in the second interruption.

5. The silicon on insulator shaped structure according to claim 4 further comprising a trench capacitor, that is in communication with at least one of the source or the drain.

6. An integrated circuit comprising:

a semiconductor substrate;

a well region formed in the substrate;

a first oxide layer overlying the substrate;

a first trench disposed throughout the first oxide layer over the well region;

a nitride layer overlying the first oxide layer;

a second oxide layer overlying the nitride layer;

a second trench disposed throughout the second oxide layer, over the well region and continuous with the first trench, the second trench being wider than the first trench;

a silicon region extending through the first trench and the second trench, the silicon region electrically contacting the well region and overlying first and second ledge portions of the first oxide layer, an upper surface of the silicon region being substantially co-planar with an upper surface of the second oxide layer;

a source disposed In the silicon region over the first ledge portion;

a drain disposed in the silicon region over the second ledge portion;

a channel disposed in the silicon region between the source and the drain, at least a portion of the channel overlying the first trench; and

a gate overlying the channel.

7. The circuit of claim 6 wherein all portions of the second oxide layer overlie portions of the first oxide layer.

8. The circuit of claim 6 wherein the silicon region comprises an epitaxially grown silicon region.

9. The circuit according to claim 6, further comprising a contact plug extending through the first oxide layer, the nitride layer and the second oxide layer and contacting the well region.

10. The circuit according to claim 9, wherein the body contact comprises a conductor.

11. The circuit according to claim 10, wherein the conductor comprises a metal layer.

12. The silicon on insulator structure according to claim 9, wherein the contact plug comprises one of the group consisting of N+ and P+ doping.

13. The circuit according to claim 6, further comprising a trench capacitor electrically coupled to the silicon region.