Simulated circuit layout for low voltage, low paper and high performance type II current conveyor

• US 6,931,605 B2
• Filed: 03/28/2001
• Issued: 08/16/2005
• Est. Priority Date: 03/28/2001
• Status: Expired due to Fees

• Current Assignee: Council of Scientific & Industrial Research
• Original Assignee: Council of Scientific & Industrial Research
• Inventors: Rajput, Sher Singh, Jamuar, Sudhanshu Shekhar
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US09/820,253
• Publication Number:
  US 20020194419A1
• Time in Patent Office: 1,602 Days
• Field of Search: 716/1, 711/1, 323/315, 323/316
• US Class Current: 323/316
• CPC Class Codes: H03F 3/345 with field-effect devices H03F3/347 takes precedence

Abstract

The present invention relates to a current conveyor circuit capable of operating at very low voltages, said circuit comprising: three LVCM'"'"'s and four MOSFETS, wherein LVCM1 provides a constant bias current to flow through M3, if port X is kept open and the difference between the bias current and the injected current flows through M3 if a current is injected into port X, which gets reflected at port Z due to the action of LVCM1, M3 and M4, LVCM2 maintains the drain currents of M1 and M2 constant, and LVCM3 maintains a constant tail current in the circuit.

Claims

1. A current conveyor circuit capable of operating at very low voltages, said current conveyor circuit comprising:

a port X for providing an input current;

a port Y for providing an input voltage;

a first low voltage current mirror (LVCM), LVCM1, having a first output port coupled to the port X and a second output port coupled to an output port Z;

a voltage buffer (VB) circuit, coupled between the port X and the port Y;

a second LVCM, LVCM2, coupled to the VB circuit, for maintaining constant drain currents of the VB circuit;

a third LVCM, LVCM3, coupled to the VB circuit, for maintaining a constant tail current in the VB circuit;

A third MOSFET M3, and a fourth MOSFET, M4, respectively, with gates coupled together and further coupled to an output port of LVCM2;

a reference voltage provided to sources of M3 and M4, respectively;

a third MOSFET M3 drain coupled to the part X and the first output port of LVCM1, LVCM1 providing a constant bias current to flow through M3; and

a fourth MOSFET M4 drain coupled to the output port Z and the second output port of LVCM1.

2. The current conveyor circuit as claimed in claim 1, wherein the current conveyor circuit comprises of one PMOS LVCM.

3. The current conveyor circuit as claimed in claim 1, wherein LVCM2 is a PMOS LVCM.

4. The current conveyor circuit as claimed in claim 1, wherein the current conveyor circuit comprises of two NMOS LVCM'"'"'s.

5. The current conveyor circuit as claimed in claim 1, wherein LVCM1 is a single input, double output NMOS LVCM.

6. The current conveyor circuit as claimed in claim 1, wherein LVCM2 is a single input, single output NMOS LVCM.

7. The current conveyor circuit as claimed in claim 1, wherein each LVCM uses a conventional current mirror structure in conjunction with a level shifter transistor at its input port.

8. The current conveyor circuit as claimed in claim 7, wherein each LVCM imparts high swing capability.

9. The current conveyor circuit as claimed in claim 8, wherein the LVCM'"'"'s ensure maximum input and output voltage swings, giving rise to rail to rail capability to voltage transfer blocks.

10. The current conveyor circuit as claimed in claim 7, wherein an adaptive biasing technique is used in each LVCM.

11. The current conveyor circuit as claimed in claim 10, wherein the adaptive biasing technique increases input voltage swing and decreases offset current.

12. The current conveyor circuit as claimed in claim 1, wherein the VB circuit comprises:

a first MOSFET, M1, having a first gate, a first source and a first drain, the first gate coupled to the port X, the first drain coupled to an input port of LVCM2, the first source coupled to an output port of LVCM3; and

a second MOSFET, M2, having a second gate, a second source and a second drain, the second gate coupled to the port Y, the second drain coupled to the output port of LVCM2, the second source coupled to the first source of M1 and further coupled to the output port of LVCM3,

wherein M1 and M2 form a differential pair.

13. The current conveyor circuit as claimed in claim 12, wherein voltage at the port Y gets transferred to the port X due to an action of the differential pair.

14. The current conveyor circuit as claimed in claim 12, wherein the current conveyor circuit further comprises a capacitance C connected between the first drain of M1 and second gate of M2.

15. The current conveyor circuit as claimed in claim 14, wherein the capacitance is connected to provide compensation.

16. The current conveyor circuit as claimed in claim 12, wherein the current conveyor circuit further comprises a resistance connected between the first and second gates of M1 and M2, respectively.

17. The current conveyor circuit as claimed in claim 16, wherein the resistance enhances frequency response of the current conveyer circuit.

18. The current conveyor circuit as claimed in claim 1, wherein the M3 and M4 form a current mirror.

19. The current conveyor circuit as claimed in claim 1, wherein the current conveyor circuit operates at a voltage range of ±

1V.

20. The current conveyor circuit as claimed in claim 1, when the port X is open, LVCM1 provides the constant bias current to flow through M3.

21. The current conveyor circuit as claimed in claim 20, wherein a current source is provided to the port X, for providing a difference current between the constant bias current and an injected current to flow through M3, the combination of LVCM1, M3 and M4 reflecting the difference current at the port Z.