Power semiconductor device

• US 6,936,893 B2
• Filed: 10/03/2003
• Issued: 08/30/2005
• Est. Priority Date: 05/26/2003
• Status: Expired due to Term

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Masahiro, Umekawa, Shinichi, Matsuda, Tadashi, Yamaguchi, Masakazu
• Primary Examiner(s): Neims, David
• Assistant Examiner(s): Nguyen, Thinh T
• Application Number:
  US10/677,260
• Publication Number:
  US 20040238884A1
• Time in Patent Office: 697 Days
• Field of Search: 257/341, 257/133, 257/135, 257/210, 257/329, 257/327, 257/328, 257/369, 257/370
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.

Claims

1. A power semiconductor device comprising:

a semiconductor active layer;

a first base layer of a first conductivity type disposed in the active layer;

a plurality of trenches disposed in a surface of the active layer at intervals to partition a main cell and a dummy cell, and to reach the first base layer;

a collector layer of a second conductivity type disposed on the first base layer, at a position remote from the trenches;

a second base layer of the second conductivity type disposed in the main cell and on the first base layer;

an emitter layer of the first conductivity type disposed on the second base layer;

a buffer layer of the second conductivity type disposed in the dummy cell and on the first base layer;

a gate electrode disposed in each trench to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;

a collector electrode disposed on the collector layer;

an emitter electrode disposed on the second base layer and the emitter layer; and

a partition structure disposed in the surface of the active layer to electrically isolate the buffer layer from the emitter electrode,

wherein the partition structure comprises dummy cell end walls, which bridge ends of the trenches one on either end of the dummy cell and cooperate with the trenches to surround the dummy cell.

2. The device according to claim 1, wherein the dummy cell end walls comprise a partition trench disposed in the surface of the active layer.

3. The device according to claim 2, wherein the partition trench has a depth substantially the same as the trenches.

4. The device according to claim 2, further comprising a conductive layer disposed in the partition trench and wrapped in an insulating film, wherein the conductive layer is electrically connected to the gate electrode.

5. The device according to claim 2, wherein the partition trench is filled with an insulating layer.

6. The device according to claim 1, wherein the dummy cell end walls comprise a partition layer of the first conductivity type disposed in the surface of the active layer.

7. The device according to claim 1, wherein the dummy cell end walls comprise a combination of a partition trench and a partition layer of the first conductivity type, the partition trench being disposed in the surface of the active layer, and the partition layer of the first conductivity type being disposed in the active layer at a position deeper than the partition trench.

8. A power semiconductor device comprising:

a semiconductor active layer;

a first base layer of a first conductivity type disposed in the active layer;

a plurality of trenches disposed in a surface of the active layer at intervals to partition a main cell and a dummy cell, and to reach the first base layer;

a collector layer of a second conductivity type disposed on the first base layer, at a position remote from the trenches;

a second base layer of the second conductivity type disposed in the main cell and on the first base layer;

an emitter layer of the first conductivity type disposed on the second base layer;

a buffer layer of the second conductivity type disposed in the dummy cell and on the first base layer;

a gate electrode disposed in each trench to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;

a collector electrode disposed on the collector layer;

an emitter electrode disposed on the second base layer and the emitter layer; and

a partition structure disposed in the surface of the active layer to electrically isolate the buffer layer from the emitter electrode,

wherein the partition structure comprises main cell end walls, which bridge ends of the trenches one on either end of the main cell and cooperate with the trenches surround the main cell.

9. The device according to claim 8, wherein the main cell end walls comprise a partition trench disposed in the surface of the active layer.

10. The device according to claim 9, wherein the partition trench has a depth substantially the same as the trenches.

11. The device according to claim 9, further comprising a conductive layer disposed in the partition trench and wrapped in an insulating film, wherein the conductive layer is electrically connected to the gate electrode.

12. The device according to claim 9, wherein the partition trench is filled with an insulating layer.

13. The device according to claim 8, wherein the main cell end walls comprise a partition layer of the first conductivity type disposed in the surface of the active layer.

14. The device according to claim 8, wherein the main cell end walls comprise a combination of a partition trench and a partition layer of the first conductivity type, the partition trench being disposed in the surface of the active layer, and the partition layer of the first conductivity type being disposed in the active layer at a position deeper than the partition trench.

15. A power semiconductor device comprising:

a semiconductor active layer;

a first base layer of a first conductivity type disposed in the active layer;

a plurality of trenches disposed in a surface of the active layer at intervals to partition a main cell and a dummy cell, and to reach the first base layer;

a collector layer of a second conductivity type disposed on the first base layer, at a position remote from the trenches;

a second base layer of the second conductivity type disposed in the main cell and on the first base layer;

an emitter layer of the first conductivity type disposed on the second base layer;

a buffer layer of the second conductivity type disposed in the dummy cell and on the first base layer;

a gate electrode disposed in each trench to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;

a collector electrode disposed on the collector layer;

an emitter electrode disposed on the second base layer and the emitter layer; and

a partition structure disposed in the surface of the active layer to electrically isolate the buffer layer from the emitter electrode,

wherein the partition structure comprises a partition wall including a partition layer of the first conductivity type disposed in the surface of the active layer.

16. The device according to claim 15, wherein the partition layer comprises a portion integral with the first base layer.

17. The device according to claim 15, wherein the partition wall is formed of a combination of a partition trench and the partition layer of the first conductivity type, the partition trench being disposed in the surface of the active layer, and the partition layer of the first conductivity type being disposed in the active layer at a position deeper than the partition trench.

18. The device according to claim 17, wherein the partition trench has a depth substantially the same as the trenches.

19. The device according to claim 17, further comprising a conductive layer disposed in the partition trench and wrapped in an insulating film, wherein the conductive layer is electrically connected to the gate electrode.

20. The device according to claim 17, wherein the partition trench is filled with an insulating layer.