Output buffer circuit with control circuit for modifying supply voltage and transistor size

• US 6,937,059 B2
• Filed: 09/23/2003
• Issued: 08/30/2005
• Est. Priority Date: 11/30/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Lee, Peter, Satou, Takashi, Matsui, Shigezumi, Yokomizo, Gouichi
• Primary Examiner(s): Cho, James H.
• Application Number:
  US10/667,446
• Publication Number:
  US 20040070420A1
• Time in Patent Office: 707 Days
• Field of Search: 326 30- 31, 326 33- 34, 326 26- 27, 327/333
• US Class Current: 326/30
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.

Claims

1. A data processing system comprising:

a first semiconductor integrated circuit;

a second semiconductor integrated circuit;

a transmission line that connects a first external output buffer of the first semiconductor integrated circuit to the second semiconductor integrated circuit, and connects a second external output buffer of the second semiconductor integrated circuit to the first semiconductor integrated circuit; and

an external power supply circuit that generates an operational supply voltage to the first and the second external output buffers,

wherein the first semiconductor integrated circuit instructs the external power supply circuit to be able to modify a level of the operational supply voltage, and includes a first operation mode capable of selectively controlling an output transistor size of the first external output buffer according to the operational supply voltage supplied according to the instruction, and

wherein the second semiconductor integrated circuit includes a second operation mode capable of selectively controlling the output transistor size of the second external output buffer according to the operational supply voltage supplied from the external power supply circuit.

2. A data processing system according to claim 1, wherein the first semiconductor integrated circuit executes, in the first operation mode, a designation of the operational supply voltage from a lower level, and execute a selection of the output transistor size from a larger size.

3. A data processing system according to claim 1,

wherein the first and the second semiconductor integrated circuits are individually capable of detecting error rates of data transmitted thereto,

wherein in the first operation mode, the first semiconductor integrated circuit is capable of a selection-modification control of the output transistor size while increasing the operational supply voltage, until the sum of the error rates detected individually by the first and the second semiconductor integrated circuits becomes lower than a specified value, and

wherein in the second operation mode, the second semiconductor integrated circuit is capable of responding to the selection-modification control by the first semiconductor integrated circuit, and capable of the selection-modification control of the output transistor size to the operational supply voltage modified by the instruction of the first semiconductor integrated circuit.

4. A data processing system according to claim 1,

wherein the first semiconductor integrated circuit is specified as being in the first operation mode, starting with responding to a system reset until reaching an impedance matching between the transmission line and the first external output buffer, in which, in response to an arrival of a specific interval, an impedance mismatching between the transmission line and the first external output buffer is compensated by a specific amount to the matching direction, and

wherein the second semiconductor integrated circuit is specified as being in the second operation mode, starting with responding to the system reset until reaching an impedance matching between the transmission line and the second external output buffer, in which, in response to the arrival of the specific interval, an impedance mismatching between the transmission line and the second external output buffer is compensated by the specific amount to the matching direction.

5. A data processing system according to claim 4, wherein the first semiconductor integrated circuit detects the arrival of the specific interval.

6. A data processing system according to claim 1, comprising a plurality of the second semiconductor integrated circuits, wherein the plural second semiconductor integrated circuits are connected to the first semiconductor integrated circuit by individual transmission lines, and the operational supply voltage is individualized to each of the transmission lines.

7. A data processing system comprising:

a first semiconductor integrated circuit;

a second semiconductor integrated circuit; and

a transmission line that connects a first external output buffer of the first semiconductor integrated circuit to the second semiconductor integrated circuit, and connects a second external output buffer of the second semiconductor integrated circuit to the first semiconductor integrated circuit,

wherein the first semiconductor integrated circuit includes an internal power supply circuit that generates an operational supply voltage to the first and the second external output buffers, instructs the internal power supply circuit to be able to modify a level of the operational supply voltage, and includes a first operation mode capable of selectively controlling an output transistor size of the first external output buffer according to the operational supply voltage generated according to the instruction, and

wherein the second semiconductor integrated circuit includes a second operation mode capable of selectively controlling the output transistor size of the second external output buffer according to the operational supply voltage supplied from the internal power supply circuit of the first semiconductor integrated circuit.

8. A data processing system according to claim 7

wherein in the first operation mode, the first semiconductor integrated circuit selectively controls the output transistor size according to the operational supply voltage, in a direction of making an impedance matching of the transmission line and the first external output buffer, and

wherein in the second operation mode, the second semiconductor integrated circuit selectively controls the output transistor size according to the operational supply voltage, in a direction of making the impedance matching of the transmission line and the first external output buffer.

9. A data processing system according to claim 8,

wherein in the first operation mode, when it is impossible to select the output transistor size for making the impedance matching, the first semiconductor integrated circuit modifies to designate a level of the operational supply voltage, and redoes the selective control of the output transistor size, and

wherein in the second operation mode, when it is impossible to select the output transistor size for making the impedance matching, the second semiconductor integrated circuit instructs the first semiconductor integrated circuit to modify the level of the operational supply voltage, and redoes the selective control of the output transistor size according to a modified operational supply voltage.

10. A data processing system according to claim 8,

wherein in the first mode, the first semiconductor integrated circuit outputs first information to designate a level of the operational supply voltage, selectively controls the output transistor size according to the operational supply voltage answered in response to the first information, requests to modify the operational supply voltage by means of the first information to redo selecting the output transistor size when it is impossible to select the output transistor size for making the impedance matching, outputs second information to the outside, waits for third information answered from the second semiconductor integrated circuit to the second information, requests to modify the operational supply voltage by means of the first information to redo selecting the output transistor size, waits for fourth information answered from the second semiconductor integrated circuit to the second information, and completes the selective control of the output transistor size,

wherein in the second mode, the second semiconductor integrated circuit inputs the second information from the first semiconductor integrated circuit, starts the selective control of the output transistor size according to the operational supply voltage by responding to the second information, outputs the third information to the first semiconductor integrated circuit when it is impossible to select the output transistor size for making the impedance matching, and outputs the fourth information to the first semiconductor integrated circuit when it is possible to select the output transistor size for making the impedance matching.

11. A data processing system according to claim 7 wherein the first semiconductor integrated circuit executes, in the first operation mode, a designation of the operational supply voltage from a lower level, and execute a selection of the output transistor size from a larger size.

12. A data processing system according to claim 7,

wherein the first and the second semiconductor integrated circuits are individually capable of detecting error rates of data transmitted thereto,

wherein in the first operation mode, the first semiconductor integrated circuit is capable of a selection-modification control of the output transistor size while increasing the operational supply voltage, until the sum of the error rates detected individually by the first and the second semiconductor integrated circuits becomes lower than a specified value, and

wherein in the second operation mode, the second semiconductor integrated circuit is capable of responding to the selection-modification control by the first semiconductor integrated circuit, and capable of the selection-modification control of the output transistor size to the operational supply voltage modified by the instruction of the first semiconductor integrated circuit.

13. A data processing system according to claim 7,

wherein the first semiconductor integrated circuit is specified as being in the first operation mode, starting with responding to a system reset until reaching an impedance matching between the transmission line and the first external output buffer, in which, in response to an arrival of a specific interval, an impedance mismatching between the transmission line and the first external output buffer is compensated by a specific amount to the matching direction, and

wherein the second semiconductor integrated circuit is specified as being in the second operation mode, starting with responding to the system reset until reaching an impedance matching between the transmission line and the second external output buffer, in which, in response to the arrival of the specific interval, an impedance mismatching between the transmission line and the second external output buffer is compensated by the specific amount to the matching direction.

14. A data processing system according to claim 13, wherein the first semiconductor integrated circuit detects the arrival of the specific interval.

15. A data processing system according to claim 7, comprising a plurality of the second semiconductor integrated circuits, wherein the plural second semiconductor integrated circuits are connected to the first semiconductor integrated circuit by individual transmission lines, and the operational supply voltage is individualized to each of the transmission lines.