Current-controlled CMOS logic family

• US 6,937,080 B2
• Filed: 05/09/2002
• Issued: 08/30/2005
• Est. Priority Date: 06/28/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hairapetian, Armond
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US10/142,450
• Publication Number:
  US 20020130692A1
• Time in Patent Office: 1,209 Days
• Field of Search: 327199-203, 327210-215, 327/219, 327/223, 327/228, 327/229, 327/230, 327/333, 327/391, 326 93- 98, 326/104, 326/115, 326/119, 326/62, 326/63, 326/68, 326/80, 326/81
• US Class Current: 327/210
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. A current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:

a clocked latch including;

first and second n-channel MOSFETs having their source terminals connected together, their gate terminals coupled to receive a first pair of differential logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively;

a first clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the first and second n-channel MOSFETs, a gate terminal coupled to receive a first clock signal CK, and a source terminal;

third and fourth n-channel MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output;

a second clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the third and fourth n-channel MOSFETs, a gate terminal coupled to receive a second clock signal CKB, and a source terminal;

first and second resistive elements respectively coupling the true output and the complementary output to a logic high level; and

a first current-source n-channel MOSFET coupled between the source terminals of the first and second clocked n-channel MOSFETs and a logic low level; and

a level shifter coupled to the first clocked latch, the level shifter including;

fifth and sixth n-channel MOSFETs having their source terminals coupled together, their gate terminals respectively coupled to receive a second pair of differential logic signals being the true output and the complementary output of the first clocked latch, and their drain terminals coupled to a common node via a respective pair of resistive loads;

a level shift resistive element coupled between the common node and the logic high level; and

a second current-source n-channel MOSFET coupled between the source terminals of the fifth and sixth n-channel MOSFETs and the logic low level,

wherein, the drain terminal of the fifth n-channel MOSFET provides a true output of the level shifter and the drain terminal of the sixth n-channel MOSFET provides the complementary output of the level shifter.

2. The circuit of claim 1 wherein the first and second resistive elements are constructed from substantially polysilicon material.

3. The circuit of claim 1 further comprising:

a buffer/inverter coupled to the level shifter and including;

seventh and eighth n-channel MOSFETs having their source terminals coupled together, their gate terminals respectively coupled to receive a third pair of differential logic signals being the true output and the complementary output of the level shifter, and their drain terminals coupled to the logic high level via at least one additional respective pair of resistive loads; and

a third current-source n-channel MOSFET coupled between the source terminals of the seventh and eighth n-channel MOSFETs and a logic low level,

wherein, the drain terminal of the seventh n-channel MOSFET provides a true output of the buffer/inverter and the drain terminal of the eighth n-channel MOSFET provides the complementary output of the buffer/inverter.

4. The circuit of claim 1 further comprising a second clocked latch similarly constructed as the first clocked latch and coupled to the level shifter, wherein gate terminals of the first and second n-channel MOSFETs in the second clocked latch respectively couple to the true output and the complementary output of the level shifter.

5. The circuit of claim 1 further comprising a logic gate coupled to the level shifter, the logic gate including:

seventh and eighth n-channel MOSFETs having their source terminals coupled to a first node, their gate terminals coupled to receive a third pair of differential logic signals being the true output and the complementary output of the level shifter, respectively, and their drain terminals connected to a true output and a complementary output of the logic gate, respectively;

ninth and tenth n-channel MOSFETs having their source terminals coupled to a second node, their gate terminals coupled to receive a fourth pair of differential logic signals, respectively, and their drain terminals coupled to the first node and one of either the true output or the complementary output, respectively;

third and fourth resistive elements respectively coupling the true output and the complementary output of the logic gate to the logic high level; and

a third current-source n-channel MOSFET coupled between the second node and a logic low level,

wherein, the logic gate implements one of AND/NAND gate or OR/NOR gate depending on logic polarity of the third pair of differential logic signals applied to the gate terminals of the seventh and eighth n-channel MOSFETs and logic polarity of the fourth pair of differential logic signals applied to the gate terminals of the ninth and tenth n-channel MOSFETs, respectively.

6. The circuit of claim 5 wherein the first, second, third and fourth resistive elements are constructed from substantially polysilicon material.

7. The circuit of claim 5 wherein the logic gate further comprises a dummy load MOSFET having a first source/drain terminal coupled to the true output or complementary output of the logic gate, and a second source/drain terminal and gate terminal coupled to a reference signal.

8. The circuit of claim 7 wherein the reference signal is the logic low level.

9. A current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:

a first clocked latch including;

first and second n-channel MOSFETs having their source terminals connected together, their gate terminals coupled to receive a first pair of differential logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively;

a first clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the first and second n-channel MOSFETs, a gate terminal coupled to receive a first clock signal CK, and a source terminal;

third and fourth n-channel MOSFETs having their source terminals coupled together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output;

a second clocked n-channel MOSFET having a drain terminal coupled to the source terminals of the third and fourth n-channel MOSFETs, a gate terminal coupled to receive a second clock signal CKB, and a source terminal;

first and second resistive elements respectively coupling the true output and the complementary output to a logic high level; and

a first current-source n-channel MOSFET coupled between the source terminals of the first and second clocked n-channel MOSFETs and a logic low level; and

a logic gate coupled to the first clocked latch, the logic gate including;

a fifth and sixth n-channel MOSFETs having their source terminals coupled to a first node, their gate terminals coupled to receive a third pair of differential logic signals being the true output and the complementary output of the first clocked latch, respectively, and their drain terminals connected to a true output and a complementary output of the logic gate;

respectively;

seventh and eighth n-channel MOSFETs having their source terminals coupled to a second node, their gate terminals coupled to receive a second pair of differential logic signals, respectively, and their drain terminals coupled to the first node and one of the either the true output or the complementary output of the logic gate, respectively;

third and fourth resistive elements respectively coupling the true output and the complementary output of the logic gate to a logic high level; and

a second current-source n-channel MOSFET coupled between the second node and the logic low level,

wherein, the logic gate implements one of AND/NAND gate or OR/NOR gate depending on logic polarity of the second pair of differential logic signals applied to the gate terminals of the seventh and eighth n-channel MOSFETs and logic polarity of the third pair of differential logic signals applied to the gate terminals of the fifth and sixth n-channel MOSFETs, respectively.

10. The circuit of claim 9 wherein the first, second, third and fourth resistive elements are constructed from substantially polysilicon material.

11. A current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:

a clocked latch including;

a first and second n-channel MOSFETs having their source terminals connected to a first node, their gate terminals coupled to receive a pair of differential logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively;

a first clocked p-channel MOSFET having a drain terminal coupled to the first node, a gate terminal coupled to receive a first clock signal CK, and a source terminal coupled to a logic high level;

a first current source device coupled between the first node and a logic low level;

third and fourth n-channel MOSFETs having their source terminals coupled to a second node, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output;

a second clocked p-channel MOSFET having a drain terminal coupled to the second node, a gate terminal coupled to receive a second clock signal CKB, and a source terminal coupled to the logic high level;

a second current source device coupled between the second node and the logic low level; and

first and second resistive elements respectively coupling the true output and the complementary output to the logic high level.

12. The circuit of claim 11 wherein the first and second resistive elements are constructed from substantially polysilicon material.